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1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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22 #include "IceTargetLowering.h" | 22 #include "IceTargetLowering.h" |
23 | 23 |
24 namespace Ice { | 24 namespace Ice { |
25 | 25 |
26 class TargetMIPS32 : public TargetLowering { | 26 class TargetMIPS32 : public TargetLowering { |
27 TargetMIPS32() = delete; | 27 TargetMIPS32() = delete; |
28 TargetMIPS32(const TargetMIPS32 &) = delete; | 28 TargetMIPS32(const TargetMIPS32 &) = delete; |
29 TargetMIPS32 &operator=(const TargetMIPS32 &) = delete; | 29 TargetMIPS32 &operator=(const TargetMIPS32 &) = delete; |
30 | 30 |
31 public: | 31 public: |
| 32 static void staticInit(); |
32 // TODO(jvoung): return a unique_ptr. | 33 // TODO(jvoung): return a unique_ptr. |
33 static TargetMIPS32 *create(Cfg *Func) { return new TargetMIPS32(Func); } | 34 static TargetMIPS32 *create(Cfg *Func) { return new TargetMIPS32(Func); } |
34 | 35 |
35 void translateOm1() override; | 36 void translateOm1() override; |
36 void translateO2() override; | 37 void translateO2() override; |
37 bool doBranchOpt(Inst *I, const CfgNode *NextNode) override; | 38 bool doBranchOpt(Inst *I, const CfgNode *NextNode) override; |
38 | 39 |
39 SizeT getNumRegisters() const override { return RegMIPS32::Reg_NUM; } | 40 SizeT getNumRegisters() const override { return RegMIPS32::Reg_NUM; } |
40 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; | 41 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; |
41 IceString getRegName(SizeT RegNum, Type Ty) const override; | 42 IceString getRegName(SizeT RegNum, Type Ty) const override; |
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190 void doAddressOptStore() override; | 191 void doAddressOptStore() override; |
191 void randomlyInsertNop(float Probability, | 192 void randomlyInsertNop(float Probability, |
192 RandomNumberGenerator &RNG) override; | 193 RandomNumberGenerator &RNG) override; |
193 void | 194 void |
194 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation, | 195 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation, |
195 const llvm::SmallBitVector &ExcludeRegisters, | 196 const llvm::SmallBitVector &ExcludeRegisters, |
196 uint64_t Salt) const override; | 197 uint64_t Salt) const override; |
197 | 198 |
198 bool UsesFramePointer = false; | 199 bool UsesFramePointer = false; |
199 bool NeedsStackAlignment = false; | 200 bool NeedsStackAlignment = false; |
200 llvm::SmallBitVector TypeToRegisterSet[IceType_NUM]; | 201 static llvm::SmallBitVector TypeToRegisterSet[IceType_NUM]; |
201 llvm::SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM]; | 202 static llvm::SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM]; |
202 llvm::SmallBitVector ScratchRegs; | 203 static llvm::SmallBitVector ScratchRegs; |
203 llvm::SmallBitVector RegsUsed; | 204 llvm::SmallBitVector RegsUsed; |
204 VarList PhysicalRegisters[IceType_NUM]; | 205 VarList PhysicalRegisters[IceType_NUM]; |
205 | 206 |
206 private: | 207 private: |
207 ~TargetMIPS32() override = default; | 208 ~TargetMIPS32() override = default; |
208 }; | 209 }; |
209 | 210 |
210 class TargetDataMIPS32 final : public TargetDataLowering { | 211 class TargetDataMIPS32 final : public TargetDataLowering { |
211 TargetDataMIPS32() = delete; | 212 TargetDataMIPS32() = delete; |
212 TargetDataMIPS32(const TargetDataMIPS32 &) = delete; | 213 TargetDataMIPS32(const TargetDataMIPS32 &) = delete; |
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245 protected: | 246 protected: |
246 explicit TargetHeaderMIPS32(GlobalContext *Ctx); | 247 explicit TargetHeaderMIPS32(GlobalContext *Ctx); |
247 | 248 |
248 private: | 249 private: |
249 ~TargetHeaderMIPS32() = default; | 250 ~TargetHeaderMIPS32() = default; |
250 }; | 251 }; |
251 | 252 |
252 } // end of namespace Ice | 253 } // end of namespace Ice |
253 | 254 |
254 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H | 255 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H |
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