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1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// | 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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153 if (Flags.getTargetInstructionSet() != | 153 if (Flags.getTargetInstructionSet() != |
154 TargetInstructionSet::BaseInstructionSet) { | 154 TargetInstructionSet::BaseInstructionSet) { |
155 InstructionSet = static_cast<ARM32InstructionSet>( | 155 InstructionSet = static_cast<ARM32InstructionSet>( |
156 (Flags.getTargetInstructionSet() - | 156 (Flags.getTargetInstructionSet() - |
157 TargetInstructionSet::ARM32InstructionSet_Begin) + | 157 TargetInstructionSet::ARM32InstructionSet_Begin) + |
158 ARM32InstructionSet::Begin); | 158 ARM32InstructionSet::Begin); |
159 } | 159 } |
160 } | 160 } |
161 | 161 |
162 TargetARM32::TargetARM32(Cfg *Func) | 162 TargetARM32::TargetARM32(Cfg *Func) |
163 : TargetLowering(Func), CPUFeatures(Func->getContext()->getFlags()) { | 163 : TargetLowering(Func), CPUFeatures(Func->getContext()->getFlags()) {} |
164 // TODO: Don't initialize IntegerRegisters and friends every time. Instead, | 164 |
165 // initialize in some sort of static initializer for the class. | 165 void TargetARM32::staticInit() { |
166 // Limit this size (or do all bitsets need to be the same width)??? | 166 // Limit this size (or do all bitsets need to be the same width)??? |
167 llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM); | 167 llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM); |
168 llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM); | 168 llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM); |
169 llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM); | 169 llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM); |
170 llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM); | 170 llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM); |
171 llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM); | 171 llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM); |
172 llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM); | 172 llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM); |
173 ScratchRegs.resize(RegARM32::Reg_NUM); | 173 ScratchRegs.resize(RegARM32::Reg_NUM); |
174 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ | 174 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ |
175 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ | 175 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
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4261 << ".eabi_attribute 42, 1 @ Tag_MPextension_use\n" | 4261 << ".eabi_attribute 42, 1 @ Tag_MPextension_use\n" |
4262 << ".eabi_attribute 68, 1 @ Tag_Virtualization_use\n"; | 4262 << ".eabi_attribute 68, 1 @ Tag_Virtualization_use\n"; |
4263 if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) { | 4263 if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) { |
4264 Str << ".eabi_attribute 44, 2 @ Tag_DIV_use\n"; | 4264 Str << ".eabi_attribute 44, 2 @ Tag_DIV_use\n"; |
4265 } | 4265 } |
4266 // Technically R9 is used for TLS with Sandboxing, and we reserve it. | 4266 // Technically R9 is used for TLS with Sandboxing, and we reserve it. |
4267 // However, for compatibility with current NaCl LLVM, don't claim that. | 4267 // However, for compatibility with current NaCl LLVM, don't claim that. |
4268 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; | 4268 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; |
4269 } | 4269 } |
4270 | 4270 |
| 4271 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM]; |
| 4272 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; |
| 4273 llvm::SmallBitVector TargetARM32::ScratchRegs; |
| 4274 |
4271 } // end of namespace Ice | 4275 } // end of namespace Ice |
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