Subzero: Refactor some common TargetLowering initializations.

src/IceTargetLoweringX86Base.h

 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 40 matching lines @@
   TargetX86Base() = delete;
   TargetX86Base(const TargetX86Base &) = delete;
   TargetX86Base &operator=(const TargetX86Base &) = delete;
 
 public:
   using Traits = MachineTraits<Machine>;
   using BoolFolding = ::Ice::X86Internal::BoolFolding<Traits>;
 
   ~TargetX86Base() override = default;
 
+  static void staticInit();

[John, 2015/11/04 21:35:23]

optional: You may want to move this to the actual target (i.e., TargetX8632)
instead. If you do, you can remove the Traits function that initializes the
register set.

[Jim Stichnoth, 2015/11/04 23:51:39]

Acknowledged.

   static TargetX86Base *create(Cfg *Func) { return new TargetX86Base(Func); }
 
   void translateOm1() override;
   void translateO2() override;
   void doLoadOpt();
   bool doBranchOpt(Inst *I, const CfgNode *NextNode) override;
 
   SizeT getNumRegisters() const override {
     return Traits::RegisterSet::Reg_NUM;
   }
@@ skipping 591 matching lines @@
 
   bool optimizeScalarMul(Variable *Dest, Operand *Src0, int32_t Src1);
   void findRMW();
 
   typename Traits::InstructionSet InstructionSet =
       Traits::InstructionSet::Begin;
   bool IsEbpBasedFrame = false;
   bool NeedsStackAlignment = false;
   size_t SpillAreaSizeBytes = 0;
   size_t FixedAllocaSizeBytes = 0;
-  std::array<llvm::SmallBitVector, IceType_NUM> TypeToRegisterSet;
-  std::array<llvm::SmallBitVector, Traits::RegisterSet::Reg_NUM>
+  static std::array<llvm::SmallBitVector, IceType_NUM> TypeToRegisterSet;
+  static std::array<llvm::SmallBitVector, Traits::RegisterSet::Reg_NUM>
       RegisterAliases;
-  llvm::SmallBitVector ScratchRegs;
+  static llvm::SmallBitVector ScratchRegs;
   llvm::SmallBitVector RegsUsed;
   std::array<VarList, IceType_NUM> PhysicalRegisters;
 
   /// Randomize a given immediate operand
   Operand *randomizeOrPoolImmediate(Constant *Immediate,
                                     int32_t RegNum = Variable::NoRegister);
   typename Traits::X86OperandMem *
   randomizeOrPoolImmediate(typename Traits::X86OperandMem *MemOperand,
                            int32_t RegNum = Variable::NoRegister);
   bool RandomizationPoolingPaused = false;
@@ skipping 49 matching lines @@
   lowerIcmp64(const InstIcmp *Icmp, const InstBr *Br);
 
   BoolFolding FoldingInfo;
 };
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #include "IceTargetLoweringX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H