Instrinsics on object pool architectures must preserve CODE_REG.

runtime/vm/flow_graph_allocator.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/flow_graph_allocator.h"
 
 #include "vm/bit_vector.h"
 #include "vm/intermediate_language.h"
 #include "vm/il_printer.h"
 #include "vm/flow_graph.h"
@@ skipping 97 matching lines @@
   }
 
   // FpuTMP is used as scratch by optimized code and parallel move resolver.
   blocked_fpu_registers_[FpuTMP] = true;
 
   // Block additional registers needed preserved when generating intrinsics.
   // TODO(fschneider): Handle saving and restoring these registers when
   // generating intrinsic code.
   if (intrinsic_mode) {
     blocked_cpu_registers_[ARGS_DESC_REG] = true;
+#if !defined(TARGET_ARCH_IA32)
+    // Need to preserve CODE_REG to be able to store the PC marker
+    // and load the pool pointer.
+    blocked_cpu_registers_[CODE_REG] = true;
+#endif
   }
 }
 
 
 static void DeepLiveness(MaterializeObjectInstr* mat, BitVector* live_in) {
   if (mat->was_visited_for_liveness()) {
     return;
   }
   mat->mark_visited_for_liveness();
 
@@ skipping 2878 matching lines @@
     THR_Print("-- [after ssa allocator] ir [%s] -------------\n",
               function.ToFullyQualifiedCString());
     FlowGraphPrinter printer(flow_graph_, true);
     printer.PrintBlocks();
     THR_Print("----------------------------------------------\n");
   }
 }
 
 
 }  // namespace dart