Add hybrid assembler concept to ARM assembler.

tests_lit/assembler/arm32/sub.ll

Index: tests_lit/assembler/arm32/sub.ll
diff --git a/tests_lit/assembler/arm32/sub.ll b/tests_lit/assembler/arm32/sub.ll
index 138f7bda9fe39eb2b7292d180a6c42b0aaad3030..1ee0b33900fa6f90218d72b40f80be1d9a1b9be4 100644
--- a/tests_lit/assembler/arm32/sub.ll
+++ b/tests_lit/assembler/arm32/sub.ll
@@ -1,14 +1,23 @@
 ; Show that we know how to translate instruction sub.
 
-; NOTE: We use -O2 to get rid of memory stores.
-
 ; REQUIRES: allow_dump
 
+; Compile using standalone assembler.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
 ; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
 ; RUN:   | FileCheck %s --check-prefix=IASM
 
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
 define internal i32 @sub1FromR0(i32 %p) {
   %v = sub i32 %p, 1
   ret i32 %v
@@ -18,6 +27,9 @@ define internal i32 @sub1FromR0(i32 %p) {
 ; ASM:	sub	r0, r0, #1
 ; ASM:	bx	lr
 
+; DIS-LABEL:00000000 <sub1FromR0>:
+; DIS-NEXT:   0:	e2400001
+
 ; IASM-LABEL: sub1FromR0:
 ; IASM:	     .byte 0x1
 ; IASM-NEXT: .byte 0x0
@@ -34,9 +46,11 @@ define internal i32 @Sub2Regs(i32 %p1, i32 %p2) {
 ; ASM:       sub r0, r0, r1
 ; ASM-NEXT:  bx lr
 
-; IASM-LABEL: Sub2Regs:
+; DIS-LABEL:00000010 <Sub2Regs>:
+; DIS-NEXT:  10:	e0400001
 
-; IASM:      .byte 0x1
+; IASM-LABEL: Sub2Regs:
+; IASM-NEXT: .byte 0x1
 ; IASM-NEXT: .byte 0x0
 ; IASM-NEXT: .byte 0x40
 ; IASM-NEXT: .byte 0xe0