Add hybrid assembler concept to ARM assembler.

src/IceAssemblerARM32.h

Index: src/IceAssemblerARM32.h
diff --git a/src/IceAssemblerARM32.h b/src/IceAssemblerARM32.h
index 4f2495c584c059f57b71409e496c0461584a00c9..9a242a04e9b9c8f8cdbf39e1a6376c64f30e0036 100644
--- a/src/IceAssemblerARM32.h
+++ b/src/IceAssemblerARM32.h
@@ -38,6 +38,21 @@
 namespace Ice {
 namespace ARM32 {
 
+/// Extends a fixup to be a textual, instruction fixup. That is, it emits text
+/// containing an instruction. This class is used to implement unimplemented
+/// emitIAS methods, allowing them to generate compilable assembly code.
+class TextInstFixup : public AssemblerFixup {
+public:
+  TextInstFixup(const std::string &Message)
+      : AssemblerFixup(), Message(Message) {}
+  ~TextInstFixup() = default;
+  virtual size_t emit(GlobalContext *Ctx, RelocOffsetT OverrideOffset,
+                      bool isPcRel) const;
+
+private:
+  std::string Message;

[Jim Stichnoth, 2015/10/20 16:28:27]

Can/should this be const?

[Karl, 2015/10/20 21:29:31]

Done.

+};
+
 class AssemblerARM32 : public Assembler {
   AssemblerARM32(const AssemblerARM32 &) = delete;
   AssemblerARM32 &operator=(const AssemblerARM32 &) = delete;
@@ -91,33 +106,37 @@ public:
 
   bool fixupIsPCRel(FixupKind Kind) const override {
     (void)Kind;
-    llvm_unreachable("Not yet implemented.");
+    // TODO(kschimpf) Decide if we need this.
+    return false;
   }
 
   void bind(Label *label);
 
-  // List of instructions implemented by integrated assembler.
+  // List of instructions implemented by integrated assembler. Returns true
+  // if able to generate corresponding instruction from given arguments.
 
-  void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
+  bool add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
-  void bkpt(uint16_t Imm16);
+  bool bkpt(uint16_t Imm16);
 
-  void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
+  bool ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
 
-  void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
+  bool mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
 
-  void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
+  bool bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
 
-  void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
+  bool str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
 
-  void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
+  bool sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   static bool classof(const Assembler *Asm) {
     return Asm->getKind() == Asm_ARM32;
   }
 
+  void emitTextInst(const std::string &Text);
+
 private:
   // A vector of pool-allocated x86 labels for CFG nodes.
   using LabelVector = std::vector<Label *>;