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Side by Side Diff: tests_lit/assembler/arm32/add.ll

Issue 1418523002: Add hybrid assembler concept to ARM assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nits. Created 5 years, 1 month ago
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1 ; Show that we know how to translate add. 1 ; Show that we know how to translate add.
2 2
3 ; NOTE: We use -O2 to get rid of memory stores. 3 ; NOTE: We use -O2 to get rid of memory stores.
4 4
5 ; REQUIRES: allow_dump 5 ; REQUIRES: allow_dump
6 6
7 ; Compile using standalone assembler.
7 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ 8 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
8 ; RUN: | FileCheck %s --check-prefix=ASM 9 ; RUN: | FileCheck %s --check-prefix=ASM
10
11 ; Show bytes in assembled standalone code.
12 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
13 ; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
14
15 ; Compile using integrated assembler.
9 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \ 16 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
10 ; RUN: | FileCheck %s --check-prefix=IASM 17 ; RUN: | FileCheck %s --check-prefix=IASM
11 18
19 ; Show bytes in assembled integrated code.
20 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
21 ; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
22
12 define internal i32 @add1ToR0(i32 %p) { 23 define internal i32 @add1ToR0(i32 %p) {
13 %v = add i32 %p, 1 24 %v = add i32 %p, 1
14 ret i32 %v 25 ret i32 %v
15 } 26 }
16 27
17 ; ASM-LABEL: add1ToR0: 28 ; ASM-LABEL: add1ToR0:
18 ; ASM: add r0, r0, #1 29 ; ASM: add r0, r0, #1
19 ; ASM-NEXT: bx lr 30 ; ASM-NEXT: bx lr
20 31
32 ; DIS-LABEL:00000000 <add1ToR0>:
33 ; DIS-NEXT: 0: e2800001
34 ; DIS-NEXT: 4: e12fff1e
35
21 ; IASM-LABEL: add1ToR0: 36 ; IASM-LABEL: add1ToR0:
22 ; IASM: .byte 0x1 37
23 ; IASM-NEXT: .byte 0x0 38 ; IASM-NEXT: .byte 0x1
24 ; IASM-NEXT: .byte 0x80 39 ; IASM-NEXT: .byte 0x0
25 ; IASM-NEXT: .byte 0xe2 40 ; IASM-NEXT: .byte 0x80
41 ; IASM-NEXT: .byte 0xe2
42
43 ; IASM-NEXT: .byte 0x1e
44 ; IASM-NEXT: .byte 0xff
45 ; IASM-NEXT: .byte 0x2f
46 ; IASM-NEXT: .byte 0xe1
26 47
27 define internal i32 @Add2Regs(i32 %p1, i32 %p2) { 48 define internal i32 @Add2Regs(i32 %p1, i32 %p2) {
28 %v = add i32 %p1, %p2 49 %v = add i32 %p1, %p2
29 ret i32 %v 50 ret i32 %v
30 } 51 }
31 52
32 ; ASM-LABEL: Add2Regs: 53 ; ASM-LABEL: Add2Regs:
33 ; ASM: add r0, r0, r1 54 ; ASM: add r0, r0, r1
34 ; ASM-NEXT: bx lr 55 ; ASM-NEXT: bx lr
35 56
57 ; DIS-LABEL:00000010 <Add2Regs>:
58 ; DIS-NEXT: 10: e0800001
59 ; DIS-NEXT: 14: e12fff1e
60
36 ; IASM-LABEL: Add2Regs: 61 ; IASM-LABEL: Add2Regs:
37 62
38 ; IASM: .byte 0x1 63 ; IASM-NEXT: .byte 0x1
39 ; IASM-NEXT: .byte 0x0 64 ; IASM-NEXT: .byte 0x0
40 ; IASM-NEXT: .byte 0x80 65 ; IASM-NEXT: .byte 0x80
41 ; IASM-NEXT: .byte 0xe0 66 ; IASM-NEXT: .byte 0xe0
67
68 ; IASM-NEXT: .byte 0x1e
69 ; IASM-NEXT: .byte 0xff
70 ; IASM-NEXT: .byte 0x2f
71 ; IASM-NEXT: .byte 0xe1
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