[mips64] Support for mips n64

src/processor/dump_context.cc

 // Copyright (c) 2010 Google Inc.
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 // notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
@@ skipping 113 matching lines @@
 const MDRawContextARM64* DumpContext::GetContextARM64() const {
   if (GetContextCPU() != MD_CONTEXT_ARM64) {
     BPLOG(ERROR) << "DumpContext cannot get arm64 context";
     return NULL;
   }
 
   return context_.arm64;
 }
 
 const MDRawContextMIPS* DumpContext::GetContextMIPS() const {
-  if (GetContextCPU() != MD_CONTEXT_MIPS) {
+  if ((GetContextCPU() != MD_CONTEXT_MIPS) &&
+      (GetContextCPU() != MD_CONTEXT_MIPS64)) {
     BPLOG(ERROR) << "DumpContext cannot get MIPS context";
     return NULL;
   }
 
   return context_.ctx_mips;
 }
 
 bool DumpContext::GetInstructionPointer(uint64_t* ip) const {
   BPLOG_IF(ERROR, !ip) << "DumpContext::GetInstructionPointer requires |ip|";
   assert(ip);
@@ skipping 20 matching lines @@
   case MD_CONTEXT_PPC64:
     *ip = GetContextPPC64()->srr0;
     break;
   case MD_CONTEXT_SPARC:
     *ip = GetContextSPARC()->pc;
     break;
   case MD_CONTEXT_X86:
     *ip = GetContextX86()->eip;
     break;
   case MD_CONTEXT_MIPS:
+  case MD_CONTEXT_MIPS64:
     *ip = GetContextMIPS()->epc;
     break;
   default:
     // This should never happen.
     BPLOG(ERROR) << "Unknown CPU architecture in GetInstructionPointer";
     return false;
   }
   return true;
 }
 
@@ skipping 23 matching lines @@
   case MD_CONTEXT_PPC64:
     *sp = GetContextPPC64()->gpr[MD_CONTEXT_PPC64_REG_SP];
     break;
   case MD_CONTEXT_SPARC:
     *sp = GetContextSPARC()->g_r[MD_CONTEXT_SPARC_REG_SP];
     break;
   case MD_CONTEXT_X86:
     *sp = GetContextX86()->esp;
     break;
   case MD_CONTEXT_MIPS:
+  case MD_CONTEXT_MIPS64:
     *sp = GetContextMIPS()->iregs[MD_CONTEXT_MIPS_REG_SP];
     break;
   default:
     // This should never happen.
     BPLOG(ERROR) << "Unknown CPU architecture in GetStackPointer";
     return false;
   }
   return true;
 }
 
@@ skipping 57 matching lines @@
 
     case MD_CONTEXT_ARM:
       delete context_.arm;
       break;
 
     case MD_CONTEXT_ARM64:
       delete context_.arm64;
       break;
 
     case MD_CONTEXT_MIPS:
+    case MD_CONTEXT_MIPS64:
       delete context_.ctx_mips;
       break;
 
     default:
       // There is no context record (valid_ is false) or there's a
       // context record for an unknown CPU (shouldn't happen, only known
       // records are stored by Read).
       break;
   }
 
@@ skipping 286 matching lines @@
       for (unsigned int freg_index = 0;
            freg_index < MD_FLOATINGSAVEAREA_ARM64_FPR_COUNT;
            ++freg_index) {
         uint128_struct fp_value = context_arm64->float_save.regs[freg_index];
         printf("  float_save.regs[%2d]            = 0x%" PRIx64 "%" PRIx64 "\n",
                freg_index, fp_value.high, fp_value.low);
       }
       break;
     }
 
-    case MD_CONTEXT_MIPS: {
+    case MD_CONTEXT_MIPS:
+    case MD_CONTEXT_MIPS64: {
       const MDRawContextMIPS* context_mips = GetContextMIPS();
       printf("MDRawContextMIPS\n");
       printf("  context_flags        = 0x%x\n",
              context_mips->context_flags);
       for (int ireg_index = 0;
            ireg_index < MD_CONTEXT_MIPS_GPR_COUNT;
            ++ireg_index) {
         printf("  iregs[%2d]           = 0x%" PRIx64 "\n",
                ireg_index, context_mips->iregs[ireg_index]);
       }
@@ skipping 33 matching lines @@
       break;
     }
 
     default: {
       break;
     }
   }
 }
 
 }  // namespace google_breakpad