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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 | 4 |
5 #include "vm/disassembler.h" | 5 #include "vm/disassembler.h" |
6 | 6 |
7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM64. | 7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM64. |
8 #if defined(TARGET_ARCH_ARM64) | 8 #if defined(TARGET_ARCH_ARM64) |
9 #include "platform/assert.h" | 9 #include "platform/assert.h" |
10 | 10 |
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76 char cur = *str++; | 76 char cur = *str++; |
77 while (cur != '\0' && (buffer_pos_ < (buffer_size_ - 1))) { | 77 while (cur != '\0' && (buffer_pos_ < (buffer_size_ - 1))) { |
78 buffer_[buffer_pos_++] = cur; | 78 buffer_[buffer_pos_++] = cur; |
79 cur = *str++; | 79 cur = *str++; |
80 } | 80 } |
81 buffer_[buffer_pos_] = '\0'; | 81 buffer_[buffer_pos_] = '\0'; |
82 } | 82 } |
83 | 83 |
84 | 84 |
85 // These register names are defined in a way to match the native disassembler | 85 // These register names are defined in a way to match the native disassembler |
86 // formatting, except for register aliases ctx (r9) and pp (r10). | 86 // formatting, except for register aliases ctx (r9), pp (r10) and sp (r19). |
87 // See for example the command "objdump -d <binary file>". | 87 // See for example the command "objdump -d <binary file>". |
88 static const char* reg_names[kNumberOfCpuRegisters] = { | 88 static const char* reg_names[kNumberOfCpuRegisters] = { |
89 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | 89 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
90 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | 90 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
91 "ip0", "ip1", "sp", "r19", "r20", "r21", "r22", "r23", | 91 "ip0", "ip1", "r18", "sp", "r20", "r21", "r22", "r23", |
92 "r24", "r25", "r26", "pp", "ctx", "fp", "lr", "r31", | 92 "r24", "r25", "r26", "pp", "ctx", "fp", "lr", "r31", |
93 }; | 93 }; |
94 | 94 |
95 | 95 |
96 // Print the register name according to the active name converter. | 96 // Print the register name according to the active name converter. |
97 void ARM64Decoder::PrintRegister(int reg, R31Type r31t) { | 97 void ARM64Decoder::PrintRegister(int reg, R31Type r31t) { |
98 ASSERT(0 <= reg); | 98 ASSERT(0 <= reg); |
99 ASSERT(reg < kNumberOfCpuRegisters); | 99 ASSERT(reg < kNumberOfCpuRegisters); |
100 if (reg == 31) { | 100 if (reg == 31) { |
101 const char* rstr = (r31t == R31IsZR) ? "zr" : "csp"; | 101 const char* rstr = (r31t == R31IsZR) ? "zr" : "csp"; |
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1461 int32_t instruction_bits = Instr::At(pc)->InstructionBits(); | 1461 int32_t instruction_bits = Instr::At(pc)->InstructionBits(); |
1462 OS::SNPrint(hex_buffer, hex_size, "%08x", instruction_bits); | 1462 OS::SNPrint(hex_buffer, hex_size, "%08x", instruction_bits); |
1463 if (out_instr_size) { | 1463 if (out_instr_size) { |
1464 *out_instr_size = Instr::kInstrSize; | 1464 *out_instr_size = Instr::kInstrSize; |
1465 } | 1465 } |
1466 } | 1466 } |
1467 | 1467 |
1468 } // namespace dart | 1468 } // namespace dart |
1469 | 1469 |
1470 #endif // defined TARGET_ARCH_ARM | 1470 #endif // defined TARGET_ARCH_ARM |
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