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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <assert.h> | 5 #include <assert.h> |
6 #include <stdarg.h> | 6 #include <stdarg.h> |
7 #include <stdio.h> | 7 #include <stdio.h> |
8 | 8 |
9 #if V8_TARGET_ARCH_X64 | 9 #if V8_TARGET_ARCH_X64 |
10 | 10 |
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951 break; | 951 break; |
952 default: | 952 default: |
953 UnimplementedInstruction(); | 953 UnimplementedInstruction(); |
954 } | 954 } |
955 } else if (vex_f3() && vex_0f()) { | 955 } else if (vex_f3() && vex_0f()) { |
956 int mod, regop, rm, vvvv = vex_vreg(); | 956 int mod, regop, rm, vvvv = vex_vreg(); |
957 get_modrm(*current, &mod, ®op, &rm); | 957 get_modrm(*current, &mod, ®op, &rm); |
958 switch (opcode) { | 958 switch (opcode) { |
959 case 0x10: | 959 case 0x10: |
960 AppendToBuffer("vmovss %s,", NameOfXMMRegister(regop)); | 960 AppendToBuffer("vmovss %s,", NameOfXMMRegister(regop)); |
| 961 if (mod == 3) { |
| 962 AppendToBuffer("%s,", NameOfXMMRegister(vvvv)); |
| 963 } |
961 current += PrintRightXMMOperand(current); | 964 current += PrintRightXMMOperand(current); |
962 break; | 965 break; |
963 case 0x11: | 966 case 0x11: |
964 AppendToBuffer("vmovss "); | 967 AppendToBuffer("vmovss "); |
965 current += PrintRightXMMOperand(current); | 968 current += PrintRightXMMOperand(current); |
| 969 if (mod == 3) { |
| 970 AppendToBuffer(",%s", NameOfXMMRegister(vvvv)); |
| 971 } |
966 AppendToBuffer(",%s", NameOfXMMRegister(regop)); | 972 AppendToBuffer(",%s", NameOfXMMRegister(regop)); |
967 break; | 973 break; |
968 case 0x58: | 974 case 0x58: |
969 AppendToBuffer("vaddss %s,%s,", NameOfXMMRegister(regop), | 975 AppendToBuffer("vaddss %s,%s,", NameOfXMMRegister(regop), |
970 NameOfXMMRegister(vvvv)); | 976 NameOfXMMRegister(vvvv)); |
971 current += PrintRightXMMOperand(current); | 977 current += PrintRightXMMOperand(current); |
972 break; | 978 break; |
973 case 0x59: | 979 case 0x59: |
974 AppendToBuffer("vmulss %s,%s,", NameOfXMMRegister(regop), | 980 AppendToBuffer("vmulss %s,%s,", NameOfXMMRegister(regop), |
975 NameOfXMMRegister(vvvv)); | 981 NameOfXMMRegister(vvvv)); |
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1002 break; | 1008 break; |
1003 default: | 1009 default: |
1004 UnimplementedInstruction(); | 1010 UnimplementedInstruction(); |
1005 } | 1011 } |
1006 } else if (vex_f2() && vex_0f()) { | 1012 } else if (vex_f2() && vex_0f()) { |
1007 int mod, regop, rm, vvvv = vex_vreg(); | 1013 int mod, regop, rm, vvvv = vex_vreg(); |
1008 get_modrm(*current, &mod, ®op, &rm); | 1014 get_modrm(*current, &mod, ®op, &rm); |
1009 switch (opcode) { | 1015 switch (opcode) { |
1010 case 0x10: | 1016 case 0x10: |
1011 AppendToBuffer("vmovsd %s,", NameOfXMMRegister(regop)); | 1017 AppendToBuffer("vmovsd %s,", NameOfXMMRegister(regop)); |
| 1018 if (mod == 3) { |
| 1019 AppendToBuffer("%s,", NameOfXMMRegister(vvvv)); |
| 1020 } |
1012 current += PrintRightXMMOperand(current); | 1021 current += PrintRightXMMOperand(current); |
1013 break; | 1022 break; |
1014 case 0x11: | 1023 case 0x11: |
1015 AppendToBuffer("vmovsd "); | 1024 AppendToBuffer("vmovsd "); |
1016 current += PrintRightXMMOperand(current); | 1025 current += PrintRightXMMOperand(current); |
| 1026 if (mod == 3) { |
| 1027 AppendToBuffer(",%s", NameOfXMMRegister(vvvv)); |
| 1028 } |
1017 AppendToBuffer(",%s", NameOfXMMRegister(regop)); | 1029 AppendToBuffer(",%s", NameOfXMMRegister(regop)); |
1018 break; | 1030 break; |
1019 case 0x2a: | 1031 case 0x2a: |
1020 AppendToBuffer("vcvtlsi2sd %s,%s,", NameOfXMMRegister(regop), | 1032 AppendToBuffer("vcvtlsi2sd %s,%s,", NameOfXMMRegister(regop), |
1021 NameOfXMMRegister(vvvv)); | 1033 NameOfXMMRegister(vvvv)); |
1022 current += PrintRightOperand(current); | 1034 current += PrintRightOperand(current); |
1023 break; | 1035 break; |
1024 case 0x2c: | 1036 case 0x2c: |
1025 AppendToBuffer("vcvttsd2si%s %s,", vex_w() ? "q" : "", | 1037 AppendToBuffer("vcvttsd2si%s %s,", vex_w() ? "q" : "", |
1026 NameOfCPURegister(regop)); | 1038 NameOfCPURegister(regop)); |
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1169 } | 1181 } |
1170 current += 1; | 1182 current += 1; |
1171 break; | 1183 break; |
1172 default: | 1184 default: |
1173 UnimplementedInstruction(); | 1185 UnimplementedInstruction(); |
1174 } | 1186 } |
1175 } else if (vex_none() && vex_0f()) { | 1187 } else if (vex_none() && vex_0f()) { |
1176 int mod, regop, rm, vvvv = vex_vreg(); | 1188 int mod, regop, rm, vvvv = vex_vreg(); |
1177 get_modrm(*current, &mod, ®op, &rm); | 1189 get_modrm(*current, &mod, ®op, &rm); |
1178 switch (opcode) { | 1190 switch (opcode) { |
| 1191 case 0x28: |
| 1192 AppendToBuffer("vmovaps %s,", NameOfXMMRegister(regop)); |
| 1193 current += PrintRightXMMOperand(current); |
| 1194 break; |
| 1195 case 0x29: |
| 1196 AppendToBuffer("vmovaps "); |
| 1197 current += PrintRightXMMOperand(current); |
| 1198 AppendToBuffer(",%s", NameOfXMMRegister(regop)); |
| 1199 break; |
1179 case 0x2e: | 1200 case 0x2e: |
1180 AppendToBuffer("vucomiss %s,", NameOfXMMRegister(regop)); | 1201 AppendToBuffer("vucomiss %s,", NameOfXMMRegister(regop)); |
1181 current += PrintRightXMMOperand(current); | 1202 current += PrintRightXMMOperand(current); |
1182 break; | 1203 break; |
1183 case 0x54: | 1204 case 0x54: |
1184 AppendToBuffer("vandps %s,%s,", NameOfXMMRegister(regop), | 1205 AppendToBuffer("vandps %s,%s,", NameOfXMMRegister(regop), |
1185 NameOfXMMRegister(vvvv)); | 1206 NameOfXMMRegister(vvvv)); |
1186 current += PrintRightXMMOperand(current); | 1207 current += PrintRightXMMOperand(current); |
1187 break; | 1208 break; |
1188 case 0x57: | 1209 case 0x57: |
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2417 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) { | 2438 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) { |
2418 fprintf(f, " "); | 2439 fprintf(f, " "); |
2419 } | 2440 } |
2420 fprintf(f, " %s\n", buffer.start()); | 2441 fprintf(f, " %s\n", buffer.start()); |
2421 } | 2442 } |
2422 } | 2443 } |
2423 | 2444 |
2424 } // namespace disasm | 2445 } // namespace disasm |
2425 | 2446 |
2426 #endif // V8_TARGET_ARCH_X64 | 2447 #endif // V8_TARGET_ARCH_X64 |
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