Chromium Code Reviews| Index: src/IceTargetLoweringMIPS32.h |
| diff --git a/src/IceTargetLoweringMIPS32.h b/src/IceTargetLoweringMIPS32.h |
| index a56aa421bd72b98a875a46910176f87646674a4c..d8c26290b3f1fa5d3d4ca516b65bdd8e6e462683 100644 |
| --- a/src/IceTargetLoweringMIPS32.h |
| +++ b/src/IceTargetLoweringMIPS32.h |
| @@ -93,10 +93,81 @@ public: |
| Context.insert(InstMIPS32Ret::create(Func, RA, Src0)); |
| } |
| + void _addiu(Variable *Dest, Variable *Src, uint32_t Imm) { |
| + Context.insert(InstMIPS32Addiu::create(Func, Dest, Src, Imm)); |
| + } |
| + |
| + void _lui(Variable *Dest, uint32_t Imm) { |
| + Context.insert(InstMIPS32Lui::create(Func, Dest, Imm)); |
| + } |
| + |
| + |
| + /// If Dest=nullptr is passed in, then a new variable is created, |
| + /// marked as infinite register allocation weight, and returned |
|
Jim Stichnoth
2015/10/18 11:48:40
Can you change "infinite register allocation weigh
rkotlerimgtec
2015/10/19 00:12:01
Done.
|
| + /// through the in/out Dest argument. |
| + void _mov(Variable *Dest, Operand *Src0 |
| + /* , int32_t RegNum = Variable::NoRegister */) { |
| + assert(Dest != nullptr); |
| + // Variable* Src0_ = llvm::dyn_cast<Variable>(Src0); |
| + if (auto C = llvm::dyn_cast<ConstantRelocatable>(Src0)) { |
| + (void)C; |
|
Jim Stichnoth
2015/10/18 11:48:40
If you don't need the value of C, change the above
rkotlerimgtec
2015/10/19 00:12:01
Done.
|
| + Context.insert(InstMIPS32La::create(Func, Dest, Src0)); |
| + } else { |
| + auto *Instr = InstMIPS32Mov::create(Func, Dest, Src0); |
| + Context.insert(Instr); |
| + if (Instr->isMultiDest()) { |
| + // If Instr is multi-dest, then Dest must be a Variable64On32. We add a |
| + // fake-def for Instr.DestHi here. |
| + assert(llvm::isa<Variable64On32>(Dest)); |
| + Context.insert(InstFakeDef::create(Func, Instr->getDestHi())); |
| + } |
| + } |
| + } |
| + |
| + void _ori(Variable *Dest, Variable *Src, uint32_t Imm) { |
| + Context.insert(InstMIPS32Ori::create(Func, Dest, Src, Imm)); |
| + } |
| + |
| void lowerArguments() override; |
| + |
| + /// Operand legalization helpers. To deal with address mode |
|
Jim Stichnoth
2015/10/18 11:48:40
Reflow this comment paragraph to 80 columns.
Actu
rkotlerimgtec
2015/10/19 00:12:01
Done.
|
| + /// constraints, the helpers will create a new Operand and emit |
| + /// instructions that guarantee that the Operand kind is one of those |
| + /// indicated by the LegalMask (a bitmask of allowed kinds). If the |
| + /// input Operand is known to already meet the constraints, it may be |
| + /// simply returned as the result, without creating any new |
| + /// instructions or operands. |
| + enum OperandLegalization { |
| + Legal_None = 0, |
| + Legal_Reg = 1 << 0, // physical register, not stack location |
| + Legal_Imm = 1 << 1, |
| + Legal_Mem = 1 << 2, |
| + Legal_All = ~Legal_None |
| + }; |
| + typedef uint32_t LegalMask; |
| + Operand *legalize(Operand *From, LegalMask Allowed = Legal_All, |
| + int32_t RegNum = Variable::NoRegister); |
| + |
| + Variable *legalizeToVar(Operand *From, int32_t RegNum = Variable::NoRegister); |
| + |
| + Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister); |
| + |
| + Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister); |
| + static Type stackSlotType(); |
| + Variable *copyToReg(Operand *Src, int32_t RegNum = Variable::NoRegister); |
| + |
| void addProlog(CfgNode *Node) override; |
| void addEpilog(CfgNode *Node) override; |
| + // Ensure that a 64-bit Variable has been split into 2 32-bit |
| + // Variables, creating them if necessary. This is needed for all |
| + // I64 operations. |
| + void split64(Variable *Var); |
| + Operand *loOperand(Operand *Operand); |
| + Operand *hiOperand(Operand *Operand); |
| + |
| + Operand *legalizeUndef(Operand *From, int32_t RegNum = Variable::NoRegister); |
| + |
| protected: |
| explicit TargetMIPS32(Cfg *Func); |
| @@ -130,8 +201,6 @@ protected: |
| const llvm::SmallBitVector &ExcludeRegisters, |
| uint64_t Salt) const override; |
| - static Type stackSlotType(); |
| - |
| bool UsesFramePointer = false; |
| bool NeedsStackAlignment = false; |
| llvm::SmallBitVector TypeToRegisterSet[IceType_NUM]; |
| @@ -177,6 +246,8 @@ public: |
| return std::unique_ptr<TargetHeaderLowering>(new TargetHeaderMIPS32(Ctx)); |
| } |
| + void lower() override; |
| + |
| protected: |
| explicit TargetHeaderMIPS32(GlobalContext *Ctx); |