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| 1 //===- subzero/src/IceRegistersMIPS32.h - Register information --*- C++ -*-===// | 1 //===- subzero/src/IceRegistersMIPS32.h - Register information --*- C++ -*-===// | 
| 2 // | 2 // | 
| 3 //                        The Subzero Code Generator | 3 //                        The Subzero Code Generator | 
| 4 // | 4 // | 
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source | 
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. | 
| 7 // | 7 // | 
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// | 
| 9 /// | 9 /// | 
| 10 /// \file | 10 /// \file | 
| 11 /// This file declares the registers and their encodings for MIPS32. | 11 /// This file declares the registers and their encodings for MIPS32. | 
| 12 /// | 12 /// | 
| 13 //===----------------------------------------------------------------------===// | 13 //===----------------------------------------------------------------------===// | 
| 14 | 14 | 
| 15 #ifndef SUBZERO_SRC_ICEREGISTERSMIPS32_H | 15 #ifndef SUBZERO_SRC_ICEREGISTERSMIPS32_H | 
| 16 #define SUBZERO_SRC_ICEREGISTERSMIPS32_H | 16 #define SUBZERO_SRC_ICEREGISTERSMIPS32_H | 
| 17 | 17 | 
| 18 #include "IceDefs.h" | 18 #include "IceDefs.h" | 
| 19 #include "IceInstMIPS32.def" | 19 #include "IceInstMIPS32.def" | 
| 20 #include "IceTypes.h" | 20 #include "IceTypes.h" | 
| 21 | 21 | 
| 22 namespace Ice { | 22 namespace Ice { | 
| 23 | 23 | 
| 24 namespace RegMIPS32 { | 24 namespace RegMIPS32 { | 
| 25 | 25 | 
| 26 /// An enum of every register. The enum value may not match the encoding | 26 /// An enum of every register. The enum value may not match the encoding | 
| 27 /// used to binary encode register operands in instructions. | 27 /// used to binary encode register operands in instructions. | 
| 28 enum AllRegisters { | 28 enum AllRegisters { | 
| 29 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \ | 29 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \ | 
| 30           isFP)                                                                \ | 30           isI64Pair, isFP32, isFP64, isVec128, alias_init)                     \ | 
| 31   val, | 31   val, | 
| 32   REGMIPS32_TABLE | 32   REGMIPS32_TABLE | 
| 33 #undef X | 33 #undef X | 
| 34       Reg_NUM, | 34       Reg_NUM, | 
| 35 #define X(val, init) val init, | 35 #define X(val, init) val init, | 
| 36   REGMIPS32_TABLE_BOUNDS | 36   REGMIPS32_TABLE_BOUNDS | 
| 37 #undef X | 37 #undef X | 
| 38 }; | 38 }; | 
| 39 | 39 | 
| 40 /// An enum of GPR Registers. The enum value does match the encoding used | 40 /// An enum of GPR Registers. The enum value does match the encoding used | 
| 41 /// to binary encode register operands in instructions. | 41 /// to binary encode register operands in instructions. | 
| 42 enum GPRRegister { | 42 enum GPRRegister { | 
| 43 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \ | 43 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \ | 
| 44           isFP)                                                                \ | 44           isI64Pair, isFP32, isFP64, isVec128, alias_init)                     \ | 
|  | 45                                                                                \ | 
| 45   Encoded_##val encode, | 46   Encoded_##val encode, | 
| 46   REGMIPS32_GPR_TABLE | 47   REGMIPS32_GPR_TABLE | 
| 47 #undef X | 48 #undef X | 
| 48       Encoded_Not_GPR = -1 | 49       Encoded_Not_GPR = -1 | 
| 49 }; | 50 }; | 
| 50 | 51 | 
| 51 // TODO(jvoung): Floating point and vector registers... | 52 // TODO(jvoung): Floating point and vector registers... | 
| 52 // Need to model overlap and difference in encoding too. | 53 // Need to model overlap and difference in encoding too. | 
| 53 | 54 | 
| 54 static inline GPRRegister getEncodedGPR(int32_t RegNum) { | 55 static inline GPRRegister getEncodedGPR(int32_t RegNum) { | 
| 55   assert(Reg_GPR_First <= RegNum && RegNum <= Reg_GPR_Last); | 56   assert(Reg_GPR_First <= RegNum && RegNum <= Reg_GPR_Last); | 
| 56   return GPRRegister(RegNum - Reg_GPR_First); | 57   return GPRRegister(RegNum - Reg_GPR_First); | 
| 57 } | 58 } | 
| 58 | 59 | 
| 59 } // end of namespace RegMIPS32 | 60 } // end of namespace RegMIPS32 | 
| 60 | 61 | 
| 61 } // end of namespace Ice | 62 } // end of namespace Ice | 
| 62 | 63 | 
| 63 #endif // SUBZERO_SRC_ICEREGISTERSMIPS32_H | 64 #endif // SUBZERO_SRC_ICEREGISTERSMIPS32_H | 
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