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Issue 1416493002: Implements simple returns and call args for Mips. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Corrections to patch set 3 per stichnot review Created 5 years, 2 months ago
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1 //===- subzero/src/IceInstMIPS32.def - X-Macros for MIPS32 insts --*- C++ -*-=== // 1 //===- subzero/src/IceInstMIPS32.def - X-Macros for MIPS32 insts --*- C++ -*-=== //
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of MIPS32 instructions in the form of x-macros. 10 // This file defines properties of MIPS32 instructions in the form of x-macros.
11 // 11 //
12 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===//
13 13
14 #ifndef SUBZERO_SRC_ICEINSTMIPS32_DEF 14 #ifndef SUBZERO_SRC_ICEINSTMIPS32_DEF
15 #define SUBZERO_SRC_ICEINSTMIPS32_DEF 15 #define SUBZERO_SRC_ICEINSTMIPS32_DEF
16 16
17 // NOTE: PC and SP are not considered isInt, to avoid register allocating. 17 // NOTE: PC and SP are not considered isInt, to avoid register allocating.
18 // TODO(reed kotler). This needs to be scrubbed and is a placeholder to get 18 // TODO(reed kotler). This needs to be scrubbed and is a placeholder to get
19 // the Mips skeleton in. 19 // the Mips skeleton in.
20 // 20 //
21 // ALIASESn is a family of macros that we use to define register aliasing in
22 // MIPS32. n indicates how many aliases are being provided to the macro. It
23 // assumes the parameters are register names declared in a namespace/class
24 // named RegMIPS32.
25 #ifndef ALIASES1
26 #define ALIASES1(r0) \
27 {RegMIPS32::r0}
28 #define ALIASES2(r0, r1) \
29 {RegMIPS32::r0, RegMIPS32::r1}
30 #define ALIASES3(r0, r1, r2) \
31 {RegMIPS32::r0, RegMIPS32::r1, RegMIPS32::r2}
32 #define ALIASES4(r0, r1, r2, r3) \
33 {RegMIPS32::r0, RegMIPS32::r1, RegMIPS32::r2, RegMIPS32::r3}
34 #define ALIASES7(r0, r1, r2, r3, r4, r5, r6) \
35 {RegMIPS32::r0, RegMIPS32::r1, RegMIPS32::r2, RegMIPS32::r3, RegMIPS32::r4,\
36 RegMIPS32::r5,RegMIPS32::r6}
37 #endif
38
21 #define REGMIPS32_GPR_TABLE \ 39 #define REGMIPS32_GPR_TABLE \
22 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, isFP */ \ 40 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
23 X(Reg_ZERO, = 0, "zero", 0, 0, 0, 0, 0, 0) \ 41 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \
24 X(Reg_AT, = Reg_ZERO + 1, "at", 1, 0, 0, 0, 1, 0) \ 42 X(Reg_ZERO, = 0, "zero", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
25 X(Reg_V0, = Reg_ZERO + 2, "v0", 1, 0, 0, 0, 1, 0) \ 43 ALIASES1(Reg_ZERO)) \
26 X(Reg_V1, = Reg_ZERO + 3, "v1", 1, 0, 0, 0, 1, 0) \ 44 X(Reg_AT, = Reg_ZERO + 1, "at", 0, 0, 0, 0, 1, 0, 0, 0, 0, \
27 X(Reg_A0, = Reg_ZERO + 4, "a0", 1, 0, 0, 0, 1, 0) \ 45 ALIASES1(Reg_AT)) \
28 X(Reg_A1, = Reg_ZERO + 5, "a1", 1, 0, 0, 0, 1, 0) \ 46 X(Reg_V0, = Reg_ZERO + 2, "v0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
29 X(Reg_A2, = Reg_ZERO + 6, "a2", 1, 0, 0, 0, 1, 0) \ 47 ALIASES2(Reg_V0, Reg_V0V1)) \
30 X(Reg_A3, = Reg_ZERO + 7, "a3", 1, 0, 0, 0, 1, 0) \ 48 X(Reg_V1, = Reg_ZERO + 3, "v1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
31 X(Reg_T0, = Reg_ZERO + 8, "t0", 1, 0, 0, 0, 1, 0) \ 49 ALIASES2(Reg_V1, Reg_V0V1)) \
32 X(Reg_T1, = Reg_ZERO + 9, "t1", 1, 0, 0, 0, 1, 0) \ 50 X(Reg_A0, = Reg_ZERO + 4, "a0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
33 X(Reg_T2, = Reg_ZERO + 10, "t2", 1, 0, 0, 0, 1, 0) \ 51 ALIASES2(Reg_A0, Reg_A0A1)) \
34 X(Reg_T3, = Reg_ZERO + 11, "t3", 1, 0, 0, 0, 1, 0) \ 52 X(Reg_A1, = Reg_ZERO + 5, "a1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
35 X(Reg_T4, = Reg_ZERO + 12, "t4", 1, 0, 0, 0, 1, 0) \ 53 ALIASES2(Reg_A1, Reg_A0A1)) \
36 X(Reg_T5, = Reg_ZERO + 14, "t5", 1, 0, 0, 0, 1, 0) \ 54 X(Reg_A2, = Reg_ZERO + 6, "a2", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
37 X(Reg_T6, = Reg_ZERO + 14, "t6", 1, 0, 0, 0, 1, 0) \ 55 ALIASES2(Reg_A2, Reg_A2A3)) \
38 X(Reg_T7, = Reg_ZERO + 15, "t7", 1, 0, 0, 0, 1, 0) \ 56 X(Reg_A3, = Reg_ZERO + 7, "a3", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
39 X(Reg_S0, = Reg_ZERO + 16, "s0", 0, 1, 0, 0, 1, 0) \ 57 ALIASES2(Reg_A3, Reg_A2A3)) \
40 X(Reg_S1, = Reg_ZERO + 17, "s1", 0, 1, 0, 0, 1, 0) \ 58 X(Reg_T0, = Reg_ZERO + 8, "t0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
41 X(Reg_S2, = Reg_ZERO + 18, "s2", 0, 1, 0, 0, 1, 0) \ 59 ALIASES2(Reg_T0, Reg_T0T1)) \
42 X(Reg_S3, = Reg_ZERO + 19, "s3", 0, 1, 0, 0, 1, 0) \ 60 X(Reg_T1, = Reg_ZERO + 9, "t1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
43 X(Reg_S4, = Reg_ZERO + 20, "s4", 0, 1, 0, 0, 1, 0) \ 61 ALIASES2(Reg_T1, Reg_T0T1)) \
44 X(Reg_S5, = Reg_ZERO + 21, "s5", 0, 1, 0, 0, 1, 0) \ 62 X(Reg_T2, = Reg_ZERO + 10, "t2", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
45 X(Reg_S6, = Reg_ZERO + 22, "s6", 0, 1, 0, 0, 1, 0) \ 63 ALIASES2(Reg_T2, Reg_T2T3)) \
46 X(Reg_S7, = Reg_ZERO + 23, "s7", 0, 1, 0, 0, 1, 0) \ 64 X(Reg_T3, = Reg_ZERO + 11, "t3", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
47 X(Reg_T8, = Reg_ZERO + 23, "t8", 1, 0, 0, 0, 1, 0) \ 65 ALIASES2(Reg_T3, Reg_T2T3)) \
48 X(Reg_T9, = Reg_ZERO + 25, "t9", 1, 0, 0, 0, 1, 0) \ 66 X(Reg_T4, = Reg_ZERO + 12, "t4", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
49 X(Reg_K0, = Reg_ZERO + 26, "k0", 0, 0, 0, 0, 0, 0) \ 67 ALIASES2(Reg_T4, Reg_T4T5)) \
50 X(Reg_K1, = Reg_ZERO + 27, "k1", 0, 0, 0, 0, 0, 0) \ 68 X(Reg_T5, = Reg_ZERO + 14, "t5", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
51 X(Reg_GP, = Reg_ZERO + 28, "gp", 0, 0, 0, 0, 0, 0) \ 69 ALIASES2(Reg_T5, Reg_T4T5)) \
52 X(Reg_SP, = Reg_ZERO + 29, "sp", 0, 0, 1, 0, 0, 0) \ 70 X(Reg_T6, = Reg_ZERO + 14, "t6", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
53 X(Reg_FP, = Reg_ZERO + 30, "fp", 0, 0, 0, 1, 0, 0) \ 71 ALIASES2(Reg_T6, Reg_T6T7)) \
54 X(Reg_RA, = Reg_ZERO + 31, "ra", 0, 1, 0, 0, 0, 0) \ 72 X(Reg_T7, = Reg_ZERO + 15, "t7", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
73 ALIASES2(Reg_T7, Reg_T6T7)) \
74 X(Reg_S0, = Reg_ZERO + 16, "s0", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
75 ALIASES2(Reg_S0, Reg_S0S1)) \
76 X(Reg_S1, = Reg_ZERO + 17, "s1", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
77 ALIASES2(Reg_S1, Reg_S0S1)) \
78 X(Reg_S2, = Reg_ZERO + 18, "s2", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
79 ALIASES2(Reg_S2, Reg_S2S3)) \
80 X(Reg_S3, = Reg_ZERO + 19, "s3", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
81 ALIASES2(Reg_S3, Reg_S2S3)) \
82 X(Reg_S4, = Reg_ZERO + 20, "s4", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
83 ALIASES2(Reg_S4, Reg_S4S5)) \
84 X(Reg_S5, = Reg_ZERO + 21, "s5", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
85 ALIASES2(Reg_S5, Reg_S4S5)) \
86 X(Reg_S6, = Reg_ZERO + 22, "s6", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
87 ALIASES2(Reg_S6, Reg_S6S7)) \
88 X(Reg_S7, = Reg_ZERO + 23, "s7", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
89 ALIASES2(Reg_S7, Reg_S6S7)) \
90 X(Reg_T8, = Reg_ZERO + 23, "t8", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
91 ALIASES2(Reg_T8, Reg_T8T9)) \
92 X(Reg_T9, = Reg_ZERO + 25, "t9", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
93 ALIASES2(Reg_T9, Reg_T8T9)) \
94 X(Reg_K0, = Reg_ZERO + 26, "k0", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
95 ALIASES1(Reg_K0)) \
96 X(Reg_K1, = Reg_ZERO + 27, "k1", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
97 ALIASES1(Reg_K1)) \
98 X(Reg_GP, = Reg_ZERO + 28, "gp", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
99 ALIASES1(Reg_GP)) \
100 X(Reg_SP, = Reg_ZERO + 29, "sp", 0, 0, 1, 0, 0, 0, 0, 0, 0, \
101 ALIASES1(Reg_SP)) \
102 X(Reg_FP, = Reg_ZERO + 30, "fp", 0, 0, 0, 1, 0, 0, 0, 0, 0, \
103 ALIASES1(Reg_FP)) \
104 X(Reg_RA, = Reg_ZERO + 31, "ra", 0, 1, 0, 0, 0, 0, 0, 0, 0, \
105 ALIASES1(Reg_RA)) \
55 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 106 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
56 // isInt, isFP) 107 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
57
58 // TODO(reed kotler): List FP registers etc. 108 // TODO(reed kotler): List FP registers etc.
59 // Be able to grab even registers, and the corresponding odd register 109 // Be able to grab even registers, and the corresponding odd register
60 // for each even register. 110 // for each even register.
111 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
112 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
113 // The following defines a table with the available pairs of consecutive i32
114 // GPRs starting at an even GPR that is not r14. Those are used to hold i64
115 // variables for atomic memory operations. If one of the registers in the pair
116 // is preserved, then we mark the whole pair as preserved to help the register
117 // allocator.
118 #define REGMIPS32_I64PAIR_TABLE \
119 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
120 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \
121 X(Reg_V0V1, 0, "v0, v1", 1, 0, 0, 0, 0, 1, 0, 0, 0, \
122 ALIASES3(Reg_V0, Reg_V1, Reg_V0V1)) \
123 X(Reg_A0A1, 2, "a0, a1", 1, 0, 0, 0, 0, 1, 0, 0, 0, \
124 ALIASES3(Reg_A0, Reg_A1, Reg_A0A1)) \
125 X(Reg_A2A3, 4, "a2, a3", 1, 0, 0, 0, 0, 1, 0, 0, 0, \
126 ALIASES3(Reg_A2, Reg_A3, Reg_A2A3)) \
127 X(Reg_T0T1, 8, "t0, t1", 1, 0, 0, 0, 0, 1, 0, 0, 0, \
128 ALIASES3(Reg_T0, Reg_T1, Reg_T0T1)) \
129 X(Reg_T2T3, 10, "t2, t3", 1, 0, 0, 0, 0, 1, 0, 0, 0, \
130 ALIASES3(Reg_T2, Reg_T3, Reg_T2T3)) \
131 X(Reg_T4T5, 12,"t4, t5", 1, 0, 0, 0, 0, 1, 0, 0, 0, \
132 ALIASES3(Reg_T4, Reg_T5, Reg_T4T5)) \
133 X(Reg_T6T7, 14, "t6, t7", 1, 0, 0, 0, 0, 1, 0, 0, 0, \
134 ALIASES3(Reg_T6, Reg_T7, Reg_T6T7)) \
135 X(Reg_S0S1, 16, "s0, s1", 0, 1, 0, 0, 0, 1, 0, 0, 0, \
136 ALIASES3(Reg_S0, Reg_S1, Reg_S0S1)) \
137 X(Reg_S2S3, 18, "s2, s3", 0, 1, 0, 0, 0, 1, 0, 0, 0, \
138 ALIASES3(Reg_S2, Reg_S3, Reg_S2S3)) \
139 X(Reg_S4S5, 20, "s4, s5", 0, 1, 0, 0, 0, 1, 0, 0, 0, \
140 ALIASES3(Reg_S4, Reg_S5, Reg_S4S5)) \
141 X(Reg_S6S7, 22, "s6, s7", 0, 1, 0, 0, 0, 1, 0, 0, 0, \
142 ALIASES3(Reg_S6, Reg_S7, Reg_S6S7)) \
143 X(Reg_T8T9, 26, "t8, t9", 1, 0, 0, 0, 0, 1, 0, 0, 0, \
144 ALIASES3(Reg_T8, Reg_T9, Reg_T8T9)) \
145 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
146 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
61 147
62 // We also provide a combined table, so that there is a namespace where 148 // We also provide a combined table, so that there is a namespace where
63 // all of the registers are considered and have distinct numberings. 149 // all of the registers are considered and have distinct numberings.
64 // This is in contrast to the above, where the "encode" is based on how 150 // This is in contrast to the above, where the "encode" is based on how
65 // the register numbers will be encoded in binaries and values can overlap. 151 // the register numbers will be encoded in binaries and values can overlap.
66 #define REGMIPS32_TABLE \ 152 #define REGMIPS32_TABLE \
67 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, isFP */ \ 153 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
68 REGMIPS32_GPR_TABLE 154 isFP32, isFP64, isVec128, alias_init */ \
155 REGMIPS32_GPR_TABLE \
156 REGMIPS32_I64PAIR_TABLE
157
69 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 158 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
70 // isInt, isFP) 159 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
71
72 #define REGMIPS32_TABLE_BOUNDS \ 160 #define REGMIPS32_TABLE_BOUNDS \
73 /* val, init */ \ 161 /* val, init */ \
74 X(Reg_GPR_First, = Reg_ZERO) \ 162 X(Reg_GPR_First, = Reg_ZERO) \
75 X(Reg_GPR_Last, = Reg_RA) 163 X(Reg_GPR_Last, = Reg_RA) \
164 X(Reg_I64PAIR_First, = Reg_V0V1) \
165 X(Reg_I64PAIR_Last, = Reg_T8T9) \
76 //define X(val, init) 166 //define X(val, init)
77 167
78 // TODO(reed kotler): add condition code tables, etc. 168 // TODO(reed kotler): add condition code tables, etc.
79 169
80 170
81 #endif // SUBZERO_SRC_ICEINSTMIPS32_DEF 171 #endif // SUBZERO_SRC_ICEINSTMIPS32_DEF
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