Implements simple returns and call args for Mips.

src/IceTargetLoweringMIPS32.h

 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 76 matching lines @@
     llvm::report_fatal_error("Not yet implemented");
   }
   void emit(const ConstantDouble *C) const final {
     (void)C;
     llvm::report_fatal_error("Not yet implemented");
   }
   void _ret(Variable *RA, Variable *Src0 = nullptr) {
     Context.insert(InstMIPS32Ret::create(Func, RA, Src0));
   }
 
+  void _addiu(Variable *Dest, Variable *Src, uint32_t Imm) {
+    Context.insert(InstMIPS32Addiu::create(Func, Dest, Src, Imm));
+  }
+
+  void _lui(Variable *Dest, uint32_t Imm) {
+    Context.insert(InstMIPS32Lui::create(Func, Dest, Imm));
+  }
+
+
+  /// If Dest=nullptr is passed in, then a new variable is created, marked as

[Jim Stichnoth, 2015/10/20 04:41:00]

Since you're following the ARM development, you should probably remove this
comment because it's incorrect (outdated).  Similarly, remove the commented-out
RegNum arg.  Also, remove one of the two blank lines above.

[rkotlerimgtec, 2015/10/21 00:30:54]

Done.

+  /// RR_MustHaveRegister, and returned through the in/out Dest argument.
+  void _mov(Variable *Dest, Operand *Src0
+            /* , int32_t RegNum = Variable::NoRegister */) {
+    assert(Dest != nullptr);
+    // Variable* Src0_ = llvm::dyn_cast<Variable>(Src0);
+    if (llvm::isa<ConstantRelocatable>(Src0)) {
+      Context.insert(InstMIPS32La::create(Func, Dest, Src0));
+    } else {
+      auto *Instr = InstMIPS32Mov::create(Func, Dest, Src0);
+      Context.insert(Instr);
+      if (Instr->isMultiDest()) {
+        // If Instr is multi-dest, then Dest must be a Variable64On32. We add a
+        // fake-def for Instr.DestHi here.
+        assert(llvm::isa<Variable64On32>(Dest));
+        Context.insert(InstFakeDef::create(Func, Instr->getDestHi()));
+      }
+    }
+  }
+
+  void _ori(Variable *Dest, Variable *Src, uint32_t Imm) {
+    Context.insert(InstMIPS32Ori::create(Func, Dest, Src, Imm));
+  }
+
   void lowerArguments() override;
+
+  /// Operand legalization helpers.  To deal with address mode constraints,
+  /// the helpers will create a new Operand and emit instructions that
+  /// guarantee that the Operand kind is one of those indicated by the
+  /// LegalMask (a bitmask of allowed kinds).  If the input Operand is known
+  /// to already meet the constraints, it may be simply returned as the result,
+  /// without creating any new instructions or operands.
+  enum OperandLegalization {
+    Legal_None = 0,
+    Legal_Reg = 1 << 0, // physical register, not stack location
+    Legal_Imm = 1 << 1,
+    Legal_Mem = 1 << 2,
+    Legal_All = ~Legal_None
+  };
+  typedef uint32_t LegalMask;
+  Operand *legalize(Operand *From, LegalMask Allowed = Legal_All,
+                    int32_t RegNum = Variable::NoRegister);
+
+  Variable *legalizeToVar(Operand *From, int32_t RegNum = Variable::NoRegister);
+
+  Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister);
+
+  Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister);
+  static Type stackSlotType();
+  Variable *copyToReg(Operand *Src, int32_t RegNum = Variable::NoRegister);
+
   void addProlog(CfgNode *Node) override;
   void addEpilog(CfgNode *Node) override;
 
+  // Ensure that a 64-bit Variable has been split into 2 32-bit
+  // Variables, creating them if necessary.  This is needed for all
+  // I64 operations.
+  void split64(Variable *Var);
+  Operand *loOperand(Operand *Operand);
+  Operand *hiOperand(Operand *Operand);
+
+  Operand *legalizeUndef(Operand *From, int32_t RegNum = Variable::NoRegister);
+
 protected:
   explicit TargetMIPS32(Cfg *Func);
 
   void postLower() override;
 
   void lowerAlloca(const InstAlloca *Inst) override;
   void lowerArithmetic(const InstArithmetic *Inst) override;
   void lowerAssign(const InstAssign *Inst) override;
   void lowerBr(const InstBr *Inst) override;
   void lowerCall(const InstCall *Inst) override;
@@ skipping 13 matching lines @@
   void prelowerPhis() override;
   void doAddressOptLoad() override;
   void doAddressOptStore() override;
   void randomlyInsertNop(float Probability,
                          RandomNumberGenerator &RNG) override;
   void
   makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation,
                                 const llvm::SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) const override;
 
-  static Type stackSlotType();
-
   bool UsesFramePointer = false;
   bool NeedsStackAlignment = false;
   llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
   llvm::SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM];
   llvm::SmallBitVector ScratchRegs;
   llvm::SmallBitVector RegsUsed;
   VarList PhysicalRegisters[IceType_NUM];
 
 private:
   ~TargetMIPS32() override = default;
@@ skipping 25 matching lines @@
 class TargetHeaderMIPS32 final : public TargetHeaderLowering {
   TargetHeaderMIPS32() = delete;
   TargetHeaderMIPS32(const TargetHeaderMIPS32 &) = delete;
   TargetHeaderMIPS32 &operator=(const TargetHeaderMIPS32 &) = delete;
 
 public:
   static std::unique_ptr<TargetHeaderLowering> create(GlobalContext *Ctx) {
     return std::unique_ptr<TargetHeaderLowering>(new TargetHeaderMIPS32(Ctx));
   }
 
+  void lower() override;
+
 protected:
   explicit TargetHeaderMIPS32(GlobalContext *Ctx);
 
 private:
   ~TargetHeaderMIPS32() = default;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H