Fixes LDR and STR instructions. Two types of mistakes were being made.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 687 matching lines @@
   IValueT Rt;
   if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Address;
   if (decodeAddress(OpAddress, Address) != DecodedAsImmRegOffset)
     return setNeedsTextFixup();
   // LDR (immediate) - ARM section A8.8.63, encoding A1:
   //   ldr<c> <Rt>, [<Rn>{, #+/-<imm12>}]      ; p=1, w=0
   //   ldr<c> <Rt>, [<Rn>], #+/-<imm12>        ; p=1, w=1
   //   ldr<c> <Rt>, [<Rn>, #+/-<imm12>]!       ; p=0, w=1
+  //
   // LDRB (immediate) - ARM section A8.8.68, encoding A1:
   //   ldrb<c> <Rt>, [<Rn>{, #+/-<imm12>}]     ; p=1, w=0
   //   ldrb<c> <Rt>, [<Rn>], #+/-<imm12>       ; p=1, w=1
   //   ldrb<c> <Rt>, [<Rn>, #+/-<imm12>]!      ; p=0, w=1
   //
   // cccc010pubw1nnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
   // iiiiiiiiiiii=imm12, b=1 if STRB, u=1 if +.
   constexpr bool IsLoad = true;
   const Type Ty = OpRt->getType();
   if (!(Ty == IceType_i32 || Ty == IceType_i8)) // TODO(kschimpf) Expand?
     return setNeedsTextFixup();
-  const bool IsByte = typeWidthInBytes(Ty) == 1;
+  const bool IsByte = isByteSizedType(Ty);
   // Check conditions of rules violated.
   if (getGPRReg(kRnShift, Address) == RegARM32::Encoded_Reg_pc)
     return setNeedsTextFixup();
   if (!isBitSet(P, Address) && isBitSet(W, Address))
     return setNeedsTextFixup();
   if (!IsByte && (getGPRReg(kRnShift, Address) == RegARM32::Encoded_Reg_sp) &&
       !isBitSet(P, Address) && isBitSet(U, Address) & !isBitSet(W, Address) &&
       (mask(Address, kImm12Shift, kImmed12Bits) == 0x8 /* 000000000100 */))
     return setNeedsTextFixup();
   emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address);
@@ skipping 136 matching lines @@
   //   strb<c> <Rt>, [<Rn>{, #+/-<imm12>}]     ; p=1, w=0
   //   strb<c> <Rt>, [<Rn>], #+/-<imm12>       ; p=1, w=1
   //   strb<c> <Rt>, [<Rn>, #+/-<imm12>]!      ; p=0, w=1
   //
   // cccc010pubw0nnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
   // iiiiiiiiiiii=imm12, b=1 if STRB, u=1 if +.
   constexpr bool IsLoad = false;
   const Type Ty = OpRt->getType();
   if (!(Ty == IceType_i32 || Ty == IceType_i8)) // TODO(kschimpf) Expand?
     return setNeedsTextFixup();
-  const bool IsByte = typeWidthInBytes(Ty) == 1;
+  const bool IsByte = isByteSizedType(Ty);
   // Check for rule violations.
   if ((getGPRReg(kRnShift, Address) == RegARM32::Encoded_Reg_pc))
     return setNeedsTextFixup();
   if (!isBitSet(P, Address) && isBitSet(W, Address))
     return setNeedsTextFixup();
   if (!IsByte && (getGPRReg(kRnShift, Address) == RegARM32::Encoded_Reg_sp) &&
       isBitSet(P, Address) && !isBitSet(U, Address) && isBitSet(W, Address) &&
       (mask(Address, kImm12Shift, kImmed12Bits) == 0x8 /* 000000000100 */))
     return setNeedsTextFixup();
   emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address);
@@ skipping 156 matching lines @@
   //   tst<c> <Rn>, #<RotatedImm8>
   //
   // cccc00110001nnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn, and
   // iiiiiiiiiiii defines RotatedImm8.
   constexpr IValueT Opcode = B3; // ie. 1000
   emitCompareOp(Opcode, OpRn, OpSrc1, Cond);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice