Add BIC(register) and BIC(immediate) to ARM integrated assembler.

tests_lit/assembler/arm32/bic.ll

Index: tests_lit/assembler/arm32/bic.ll
diff --git a/tests_lit/assembler/arm32/bic.ll b/tests_lit/assembler/arm32/bic.ll
new file mode 100644
index 0000000000000000000000000000000000000000..d30a08759d2fb24a4b6ba0725e5d8c4cddfe2773
--- /dev/null
+++ b/tests_lit/assembler/arm32/bic.ll
@@ -0,0 +1,89 @@
+; Show that we know how to translate bic.
+
+; NOTE: We use -O2 to get rid of memory stores.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
+define internal i32 @AllocBigAlign() {
+  %addr = alloca i8, align 32
+  %v = ptrtoint i8* %addr to i32
+  ret i32 %v
+}
+
+; ASM-LABEL:AllocBigAlign:
+; ASM:.LAllocBigAlign$__0:
+; ASM:  push    {fp}
+; ASM:  mov     fp, sp
+; ASM:  sub     sp, sp, #12
+; ASM:  bic     sp, sp, #31
+; ASM:  sub     sp, sp, #32
+; ASM:  mov     r0, sp
+; ASM:  mov     sp, fp
+; ASM:  pop     {fp}
+; ASM:  # fp = def.pseudo 
+; ASM:  bx      lr
+
+; DIS-LABEL:00000000 <AllocBigAlign>:
+; DIS-NEXT:   0:        e52db004
+; DIS-NEXT:   4:        e1a0b00d
+; DIS-NEXT:   8:        e24dd00c
+; DIS-NEXT:   c:        e3cdd01f
+; DIS-NEXT:  10:        e24dd020
+; DIS-NEXT:  14:        e1a0000d
+; DIS-NEXT:  18:        e1a0d00b
+; DIS-NEXT:  1c:        e49db004
+; DIS-NEXT:  20:        e12fff1e
+
+; IASM-LABEL:AllocBigAlign:
+; IASM-NEXT:.LAllocBigAlign$__0:
+; IASM:         push    {fp}
+; IASM:         .byte 0xd
+; IASM-NEXT:    .byte 0xb0
+; IASM-NEXT:    .byte 0xa0
+; IASM-NEXT:    .byte 0xe1
+
+; IASM:         .byte 0xc
+; IASM-NEXT:    .byte 0xd0
+; IASM-NEXT:    .byte 0x4d
+; IASM-NEXT:    .byte 0xe2
+
+; IASM:         .byte 0x1f
+; IASM-NEXT:    .byte 0xd0
+; IASM-NEXT:    .byte 0xcd
+; IASM-NEXT:    .byte 0xe3
+
+; IASM:         .byte 0x20
+; IASM-NEXT:    .byte 0xd0
+; IASM-NEXT:    .byte 0x4d
+; IASM-NEXT:    .byte 0xe2
+
+; IASM:         .byte 0xd
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0xa0
+; IASM-NEXT:    .byte 0xe1
+
+; IASM:         .byte 0xb
+; IASM-NEXT:    .byte 0xd0
+; IASM-NEXT:    .byte 0xa0
+; IASM-NEXT:    .byte 0xe1
+; IASM:         pop     {fp}
+; IASM:         .byte 0x1e
+; IASM-NEXT:    .byte 0xff
+; IASM-NEXT:    .byte 0x2f
+; IASM-NEXT:    .byte 0xe1