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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// | 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// |
2 // | 2 // |
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
4 // for details. All rights reserved. Use of this source code is governed by a | 4 // for details. All rights reserved. Use of this source code is governed by a |
5 // BSD-style license that can be found in the LICENSE file. | 5 // BSD-style license that can be found in the LICENSE file. |
6 // | 6 // |
7 // Modified by the Subzero authors. | 7 // Modified by the Subzero authors. |
8 // | 8 // |
9 //===----------------------------------------------------------------------===// | 9 //===----------------------------------------------------------------------===// |
10 // | 10 // |
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145 bool SetFlags, CondARM32::Cond Cond); | 145 bool SetFlags, CondARM32::Cond Cond); |
146 | 146 |
147 void b(Label *L, CondARM32::Cond Cond); | 147 void b(Label *L, CondARM32::Cond Cond); |
148 | 148 |
149 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL); | 149 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL); |
150 | 150 |
151 void bkpt(uint16_t Imm16); | 151 void bkpt(uint16_t Imm16); |
152 | 152 |
153 void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond); | 153 void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond); |
154 | 154 |
| 155 void bic(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 156 bool SetFlags, CondARM32::Cond Cond); |
| 157 |
155 void eor(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, | 158 void eor(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
156 bool SetFlags, CondARM32::Cond Cond); | 159 bool SetFlags, CondARM32::Cond Cond); |
157 | 160 |
158 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); | 161 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); |
159 | 162 |
160 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); | 163 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); |
161 | 164 |
162 void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, | 165 void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
163 bool SetFlags, CondARM32::Cond Cond); | 166 bool SetFlags, CondARM32::Cond Cond); |
164 | 167 |
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237 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst); | 240 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst); |
238 | 241 |
239 // Returns the offset encoded in the branch instruction Inst. | 242 // Returns the offset encoded in the branch instruction Inst. |
240 static IOffsetT decodeBranchOffset(IValueT Inst); | 243 static IOffsetT decodeBranchOffset(IValueT Inst); |
241 }; | 244 }; |
242 | 245 |
243 } // end of namespace ARM32 | 246 } // end of namespace ARM32 |
244 } // end of namespace Ice | 247 } // end of namespace Ice |
245 | 248 |
246 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H | 249 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H |
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