Add BIC(register) and BIC(immediate) to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 545 matching lines @@
   // BKPT - ARM section A*.8.24 - encoding A1:
   //   bkpt #<Imm16>
   //
   // cccc00010010iiiiiiiiiiii0111iiii where cccc=AL and iiiiiiiiiiiiiiii=Imm16
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = (CondARM32::AL << kConditionShift) | B24 | B21 |
                            ((Imm16 >> 4) << 8) | B6 | B5 | B4 | (Imm16 & 0xf);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::bic(const Operand *OpRd, const Operand *OpRn,
+                         const Operand *OpSrc1, bool SetFlags,
+                         CondARM32::Cond Cond) {
+  // BIC (register) - ARM section A8.8.22, encoding A1:
+  //   bic{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+  //
+  // cccc0001110snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
+  // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
+  //
+  // BIC (immediate) - ARM section A8.8.21, encoding A1:
+  //   bic{s}<c> <Rd>, <Rn>, #<RotatedImm8>
+  //
+  // cccc0011110snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rn, nnnn=Rn,
+  // s=SetFlags, and iiiiiiiiiiii=Src1Value defining RotatedImm8.
+  IValueT Opcode = B3 | B2 | B1; // i.e. 1110
+  emitType01(Opcode, OpRd, OpRn, OpSrc1, SetFlags, Cond);
+}
+
 void AssemblerARM32::bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond) {
   // BX - ARM section A8.8.27, encoding A1:
   //   bx<c> <Rm>
   //
   // cccc000100101111111111110001mmmm where mmmm=rm and cccc=Cond.
   if (!(isGPRRegisterDefined(Rm) && isConditionDefined(Cond)))
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B24 |
                            B21 | (0xfff << 8) | B4 |
@@ skipping 386 matching lines @@
   //    sub{s}<c> sp, <Rn>, #<RotatedImm8>
   //
   // cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8
   constexpr IValueT Sub = B1; // 0010
   emitType01(Sub, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice