Subzero. ARM32. Implements bool folding.

tests_lit/llvm2ice_tests/test_i1.ll

Index: tests_lit/llvm2ice_tests/test_i1.ll
diff --git a/tests_lit/llvm2ice_tests/test_i1.ll b/tests_lit/llvm2ice_tests/test_i1.ll
index b437b3109bfe8377c9709eda796dc83b160836db..18b2f0239eccf61f9350889adaf7a7bded866bef 100644
--- a/tests_lit/llvm2ice_tests/test_i1.ll
+++ b/tests_lit/llvm2ice_tests/test_i1.ll
@@ -8,17 +8,10 @@
 ; RUN:   --target x8632 -i %s --args -Om1 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
-; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented)
-; once enough infrastructure is in. Also, switch to --filetype=obj
-; when possible.
+; TODO(jpp): Switch to --filetype=obj when possible.
 ; RUN: %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command %p2i --filetype=asm --assemble \
-; RUN:   --disassemble --target arm32 -i %s --args -O2 --skip-unimplemented \
-; RUN:   | %if --need=target_ARM32 --need=allow_dump \
-; RUN:   --command FileCheck --check-prefix ARM32 %s
-; RUN: %if --need=target_ARM32 --need=allow_dump \
-; RUN:   --command %p2i --filetype=asm --assemble \
-; RUN:   --disassemble --target arm32 -i %s --args -Om1 --skip-unimplemented \
+; RUN:   --disassemble --target arm32 -i %s --args -O2 \
 ; RUN:   | %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command FileCheck --check-prefix ARM32 %s
 
@@ -73,7 +66,9 @@ entry:
 ; CHECK-LABEL: testTrunc
 ; CHECK: and {{.*}},0x1
 ; ARM32-LABEL: testTrunc
-; ARM32: and {{.*}}, #1
+; ARM32: tst r0, #1
+; ARM32: moveq [[REG:r[0-9]*]], #0
+; ARM32: movne [[REG]], #1
 
 ; Test zext to i8.
 define internal i32 @testZextI8(i32 %arg) {
@@ -89,8 +84,10 @@ entry:
 ; match the zext i1 instruction (NOTE: no mov need between i1 and i8).
 ; CHECK-NOT: and {{.*}},0x1
 ; ARM32-LABEL: testZextI8
-; ARM32: and {{.*}}, #1
-; ARM32: and {{.*}}, #1
+; ARM32: tst r0, #1
+; ARM32: moveq [[REG:r[0-9]*]], #0
+; ARM32: movne [[REG]], #1
+; ARM32: uxtb [[REG]]
 
 ; Test zext to i16.
 define internal i32 @testZextI16(i32 %arg) {
@@ -108,10 +105,10 @@ entry:
 ; CHECK-NOT: and [[REG]],0x1
 
 ; ARM32-LABEL: testZextI16
-; match the trunc instruction
-; ARM32: and {{.*}}, #1
-; match the zext (no need to uxt into a reg if src is already in a reg)
-; ARM32: and {{.*}}, #1
+; ARM32: tst r0, #1
+; ARM32: moveq [[REG:r[0-9]*]], #0
+; ARM32: movne [[REG]], #1
+; ARM32: uxth [[REG]]
 
 ; Test zext to i32.
 define internal i32 @testZextI32(i32 %arg) {
@@ -127,8 +124,9 @@ entry:
 ; CHECK: movzx
 ; CHECK-NOT: and {{.*}},0x1
 ; ARM32-LABEL: testZextI32
-; ARM32: and {{.*}}, #1
-; ARM32: and {{.*}}, #1
+; ARM32: tst r0, #1
+; ARM32: moveq [[REG:r[0-9]*]], #0
+; ARM32: movne [[REG]], #1
 
 ; Test zext to i64.
 define internal i64 @testZextI64(i32 %arg) {
@@ -144,9 +142,10 @@ entry:
 ; CHECK: movzx
 ; CHECK: mov {{.*}},0x0
 ; ARM32-LABEL: testZextI64
-; ARM32: and {{.*}}, #1
-; ARM32: and {{.*}}, #1
-; ARM32: mov {{.*}}, #0
+; ARM32: tst r0, #1
+; ARM32: mov r{{[0-9]*}}, #0
+; ARM32: moveq [[REG:r[0-9]*]], #0
+; ARM32: movne [[REG]], #1
 
 ; Test sext to i8.
 define internal i32 @testSextI8(i32 %arg) {
@@ -163,13 +162,12 @@ entry:
 ; CHECK: shl [[REG:.*]],0x7
 ; CHECK-NEXT: sar [[REG]],0x7
 ;
-; ARM shifts by 32, since there aren't any byte regs.
 ; ARM32-LABEL: testSextI8
-; match the trunc instruction
-; ARM32: and {{.*}}, #1
-; match the sext i1 instruction
-; ARM32: lsl {{.*}}, #31
-; ARM32-NEXT: asr {{.*}}, #31
+; ARM32: tst r0, #1
+; ARM32: mvn [[REG_M1:r[0-9]*]], #0
+; ARM32: moveq [[REG:r[0-9]*]], #0
+; ARM32: movne [[REG]], [[REG_M1]]
+; ARM32: sxtb [[REG]]
 
 ; Test sext to i16.
 define internal i32 @testSextI16(i32 %arg) {
@@ -188,9 +186,11 @@ entry:
 ; CHECK-NEXT: sar [[REG]],0xf
 
 ; ARM32-LABEL: testSextI16
-; ARM32: and {{.*}}, #1
-; ARM32: lsl {{.*}}, #31
-; ARM32-NEXT: asr {{.*}}, #31
+; ARM32: tst r0, #1
+; ARM32: mvn [[REG_M1:r[0-9]*]], #0
+; ARM32: moveq [[REG:r[0-9]*]], #0
+; ARM32: movne [[REG]], [[REG_M1]]
+; ARM32: sxth [[REG]]
 
 ; Test sext to i32.
 define internal i32 @testSextI32(i32 %arg) {
@@ -208,9 +208,10 @@ entry:
 ; CHECK-NEXT: sar [[REG]],0x1f
 
 ; ARM32-LABEL: testSextI32
-; ARM32: and {{.*}}, #1
-; ARM32: lsl {{.*}}, #31
-; ARM32-NEXT: asr {{.*}}, #31
+; ARM32: tst r0, #1
+; ARM32: mvn [[REG_M1:r[0-9]*]], #0
+; ARM32: moveq [[REG:r[0-9]*]], #0
+; ARM32: movne [[REG]], [[REG_M1]]
 
 ; Test sext to i64.
 define internal i64 @testSextI64(i32 %arg) {
@@ -228,10 +229,11 @@ entry:
 ; CHECK-NEXT: sar [[REG]],0x1f
 
 ; ARM32-LABEL: testSextI64
-; ARM32: and {{.*}}, #1
-; ARM32: lsl {{.*}}, #31
-; ARM32-NEXT: asr [[REG:r.*]], {{.*}}, #31
-; ARM32-NEXT: {{(mov|str).*}} [[REG]]
+; ARM32: tst r0, #1
+; ARM32: mvn [[REG_M1:r[0-9]*]], #0
+; ARM32: moveq [[REG:r[0-9]*]], #0
+; ARM32: movne [[REG]], [[REG_M1]]
+; ARM32: mov r{{[0-9]+}}, [[REG]]
 
 ; Kind of like sext i1 to i32, but with an immediate source. On ARM,
 ; sxtb cannot take an immediate operand, so make sure it's using a reg.