OLD | NEW |
1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// | 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
(...skipping 362 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
373 if (Func->hasError()) | 373 if (Func->hasError()) |
374 return; | 374 return; |
375 Func->dump("After legalizeStackSlots"); | 375 Func->dump("After legalizeStackSlots"); |
376 | 376 |
377 // Nop insertion | 377 // Nop insertion |
378 if (Ctx->getFlags().shouldDoNopInsertion()) { | 378 if (Ctx->getFlags().shouldDoNopInsertion()) { |
379 Func->doNopInsertion(); | 379 Func->doNopInsertion(); |
380 } | 380 } |
381 } | 381 } |
382 | 382 |
| 383 uint32_t TargetARM32::getStackAlignment() const { |
| 384 return ARM32_STACK_ALIGNMENT_BYTES; |
| 385 } |
| 386 |
383 bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) { | 387 bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) { |
384 if (InstARM32Br *Br = llvm::dyn_cast<InstARM32Br>(I)) { | 388 if (InstARM32Br *Br = llvm::dyn_cast<InstARM32Br>(I)) { |
385 return Br->optimizeBranch(NextNode); | 389 return Br->optimizeBranch(NextNode); |
386 } | 390 } |
387 return false; | 391 return false; |
388 } | 392 } |
389 | 393 |
390 const char *RegARM32::RegNames[] = { | 394 const char *RegARM32::RegNames[] = { |
391 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ | 395 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ |
392 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ | 396 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
(...skipping 3873 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4266 // Technically R9 is used for TLS with Sandboxing, and we reserve it. | 4270 // Technically R9 is used for TLS with Sandboxing, and we reserve it. |
4267 // However, for compatibility with current NaCl LLVM, don't claim that. | 4271 // However, for compatibility with current NaCl LLVM, don't claim that. |
4268 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; | 4272 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; |
4269 } | 4273 } |
4270 | 4274 |
4271 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM]; | 4275 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM]; |
4272 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; | 4276 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; |
4273 llvm::SmallBitVector TargetARM32::ScratchRegs; | 4277 llvm::SmallBitVector TargetARM32::ScratchRegs; |
4274 | 4278 |
4275 } // end of namespace Ice | 4279 } // end of namespace Ice |
OLD | NEW |