[turbofan] Avoid unnecessary write barriers and improve code generation.

src/compiler/arm64/instruction-codes-arm64.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
 
 namespace v8 {
 namespace internal {
 namespace compiler {
@@ skipping 111 matching lines @@
   V(Arm64StrD)                     \
   V(Arm64Ldrb)                     \
   V(Arm64Ldrsb)                    \
   V(Arm64Strb)                     \
   V(Arm64Ldrh)                     \
   V(Arm64Ldrsh)                    \
   V(Arm64Strh)                     \
   V(Arm64LdrW)                     \
   V(Arm64StrW)                     \
   V(Arm64Ldr)                      \
-  V(Arm64Str)                      \
-  V(Arm64StoreWriteBarrier)
+  V(Arm64Str)
 
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes
 // are encoded into the InstructionCode of the instruction and tell the
 // code generator after register allocation which assembler method to call.
 //
 // We use the following local notation for addressing modes:
 //
 // R = register
@@ skipping 12 matching lines @@
   V(Operand2_R_UXTB)  /* %r0 UXTB (unsigned extend byte) */     \
   V(Operand2_R_UXTH)  /* %r0 UXTH (unsigned extend halfword) */ \
   V(Operand2_R_SXTB)  /* %r0 SXTB (signed extend byte) */       \
   V(Operand2_R_SXTH)  /* %r0 SXTH (signed extend halfword) */
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_