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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
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95 V(Mips64Float64ExtractLowWord32) \ | 95 V(Mips64Float64ExtractLowWord32) \ |
96 V(Mips64Float64ExtractHighWord32) \ | 96 V(Mips64Float64ExtractHighWord32) \ |
97 V(Mips64Float64InsertLowWord32) \ | 97 V(Mips64Float64InsertLowWord32) \ |
98 V(Mips64Float64InsertHighWord32) \ | 98 V(Mips64Float64InsertHighWord32) \ |
99 V(Mips64Float64Max) \ | 99 V(Mips64Float64Max) \ |
100 V(Mips64Float64Min) \ | 100 V(Mips64Float64Min) \ |
101 V(Mips64Float32Max) \ | 101 V(Mips64Float32Max) \ |
102 V(Mips64Float32Min) \ | 102 V(Mips64Float32Min) \ |
103 V(Mips64Push) \ | 103 V(Mips64Push) \ |
104 V(Mips64StoreToStackSlot) \ | 104 V(Mips64StoreToStackSlot) \ |
105 V(Mips64StackClaim) \ | 105 V(Mips64StackClaim) |
106 V(Mips64StoreWriteBarrier) | |
107 | 106 |
108 | 107 |
109 // Addressing modes represent the "shape" of inputs to an instruction. | 108 // Addressing modes represent the "shape" of inputs to an instruction. |
110 // Many instructions support multiple addressing modes. Addressing modes | 109 // Many instructions support multiple addressing modes. Addressing modes |
111 // are encoded into the InstructionCode of the instruction and tell the | 110 // are encoded into the InstructionCode of the instruction and tell the |
112 // code generator after register allocation which assembler method to call. | 111 // code generator after register allocation which assembler method to call. |
113 // | 112 // |
114 // We use the following local notation for addressing modes: | 113 // We use the following local notation for addressing modes: |
115 // | 114 // |
116 // R = register | 115 // R = register |
117 // O = register or stack slot | 116 // O = register or stack slot |
118 // D = double register | 117 // D = double register |
119 // I = immediate (handle, external, int32) | 118 // I = immediate (handle, external, int32) |
120 // MRI = [register + immediate] | 119 // MRI = [register + immediate] |
121 // MRR = [register + register] | 120 // MRR = [register + register] |
122 // TODO(plind): Add the new r6 address modes. | 121 // TODO(plind): Add the new r6 address modes. |
123 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 122 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
124 V(MRI) /* [%r0 + K] */ \ | 123 V(MRI) /* [%r0 + K] */ \ |
125 V(MRR) /* [%r0 + %r1] */ | 124 V(MRR) /* [%r0 + %r1] */ |
126 | 125 |
127 | 126 |
128 } // namespace compiler | 127 } // namespace compiler |
129 } // namespace internal | 128 } // namespace internal |
130 } // namespace v8 | 129 } // namespace v8 |
131 | 130 |
132 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 131 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
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