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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ | 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ | 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
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86 V(ArmVstrF64) \ | 86 V(ArmVstrF64) \ |
87 V(ArmLdrb) \ | 87 V(ArmLdrb) \ |
88 V(ArmLdrsb) \ | 88 V(ArmLdrsb) \ |
89 V(ArmStrb) \ | 89 V(ArmStrb) \ |
90 V(ArmLdrh) \ | 90 V(ArmLdrh) \ |
91 V(ArmLdrsh) \ | 91 V(ArmLdrsh) \ |
92 V(ArmStrh) \ | 92 V(ArmStrh) \ |
93 V(ArmLdr) \ | 93 V(ArmLdr) \ |
94 V(ArmStr) \ | 94 V(ArmStr) \ |
95 V(ArmPush) \ | 95 V(ArmPush) \ |
96 V(ArmPoke) \ | 96 V(ArmPoke) |
97 V(ArmStoreWriteBarrier) | |
98 | 97 |
99 | 98 |
100 // Addressing modes represent the "shape" of inputs to an instruction. | 99 // Addressing modes represent the "shape" of inputs to an instruction. |
101 // Many instructions support multiple addressing modes. Addressing modes | 100 // Many instructions support multiple addressing modes. Addressing modes |
102 // are encoded into the InstructionCode of the instruction and tell the | 101 // are encoded into the InstructionCode of the instruction and tell the |
103 // code generator after register allocation which assembler method to call. | 102 // code generator after register allocation which assembler method to call. |
104 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 103 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
105 V(Offset_RI) /* [%r0 + K] */ \ | 104 V(Offset_RI) /* [%r0 + K] */ \ |
106 V(Offset_RR) /* [%r0 + %r1] */ \ | 105 V(Offset_RR) /* [%r0 + %r1] */ \ |
107 V(Operand2_I) /* K */ \ | 106 V(Operand2_I) /* K */ \ |
108 V(Operand2_R) /* %r0 */ \ | 107 V(Operand2_R) /* %r0 */ \ |
109 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ | 108 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ |
110 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ | 109 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ |
111 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ | 110 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ |
112 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ | 111 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ |
113 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ | 112 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ |
114 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ | 113 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ |
115 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ | 114 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ |
116 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ | 115 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ |
117 | 116 |
118 } // namespace compiler | 117 } // namespace compiler |
119 } // namespace internal | 118 } // namespace internal |
120 } // namespace v8 | 119 } // namespace v8 |
121 | 120 |
122 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ | 121 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
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