Fix frame pointer loads/stores in the ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 215 matching lines @@
   if (Offset < 0) {
     Value = (Value ^ U) | -Offset; // Flip U to adjust sign.
   } else {
     Value |= Offset;
   }
   return Value;
 }
 
 // Decodes memory address Opnd, and encodes that information into Value,
 // based on how ARM represents the address. Returns how the value was encoded.
-DecodedResult decodeAddress(const Operand *Opnd, IValueT &Value) {
+DecodedResult decodeAddress(const Operand *Opnd, IValueT &Value,
+                            const AssemblerARM32::TargetInfo &TInfo) {
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     // Should be a stack variable, with an offset.
     if (Var->hasReg())
       return CantDecode;
-    const IOffsetT Offset = Var->getStackOffset();
+    IOffsetT Offset = Var->getStackOffset();
     if (!Utils::IsAbsoluteUint(12, Offset))
       return CantDecode;
-    RegARM32::GPRRegister BaseReg = RegARM32::Encoded_Reg_sp;
-    if (const auto *StackVar = llvm::dyn_cast<StackVariable>(Var))
-      BaseReg = decodeGPRRegister(StackVar->getBaseRegNum());
-    Value = decodeImmRegOffset(BaseReg, Offset, OperandARM32Mem::Offset);
+    int32_t BaseRegNum = Var->getBaseRegNum();
+    if (BaseRegNum == Variable::NoRegister) {
+      BaseRegNum = TInfo.FrameOrStackReg;
+      if (!TInfo.HasFramePointer)
+        Offset += TInfo.StackAdjustment;
+    }
+    Value = decodeImmRegOffset(decodeGPRRegister(BaseRegNum), Offset,
+                               OperandARM32Mem::Offset);
     return DecodedAsImmRegOffset;
   }
   if (const auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Opnd)) {
     if (Mem->isRegReg())
       // TODO(kschimpf) Add this case.
       return CantDecode;
     Variable *Var = Mem->getBase();
     if (!Var->hasReg())
       return CantDecode;
     ConstantInteger32 *Offset = Mem->getOffset();
@@ skipping 430 matching lines @@
   // EOR (Immediate) - ARM section A8.*.46, encoding A1:
   //   eor{s}<c> <Rd>, <Rn>, #RotatedImm8
   //
   // cccc0010001snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Eor = B0; // 0001
   emitType01(Eor, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
 void AssemblerARM32::ldr(const Operand *OpRt, const Operand *OpAddress,
-                         CondARM32::Cond Cond) {
+                         CondARM32::Cond Cond, const TargetInfo &TInfo) {
   IValueT Rt;
   if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Address;
-  if (decodeAddress(OpAddress, Address) != DecodedAsImmRegOffset)
+  if (decodeAddress(OpAddress, Address, TInfo) != DecodedAsImmRegOffset)
     return setNeedsTextFixup();
   // LDR (immediate) - ARM section A8.8.63, encoding A1:
   //   ldr<c> <Rt>, [<Rn>{, #+/-<imm12>}]      ; p=1, w=0
   //   ldr<c> <Rt>, [<Rn>], #+/-<imm12>        ; p=1, w=1
   //   ldr<c> <Rt>, [<Rn>, #+/-<imm12>]!       ; p=0, w=1
   //
   // LDRB (immediate) - ARM section A8.8.68, encoding A1:
   //   ldrb<c> <Rt>, [<Rn>{, #+/-<imm12>}]     ; p=1, w=0
   //   ldrb<c> <Rt>, [<Rn>], #+/-<imm12>       ; p=1, w=1
   //   ldrb<c> <Rt>, [<Rn>, #+/-<imm12>]!      ; p=0, w=1
@@ skipping 156 matching lines @@
     return setNeedsTextFixup();
   if (Rd == RegARM32::Encoded_Reg_pc || Rn == RegARM32::Encoded_Reg_pc ||
       Rm == RegARM32::Encoded_Reg_pc)
     llvm::report_fatal_error("Sdiv instruction unpredictable on pc");
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   constexpr IValueT Opcode = 0;
   emitDivOp(Cond, Opcode, Rd, Rn, Rm);
 }
 
 void AssemblerARM32::str(const Operand *OpRt, const Operand *OpAddress,
-                         CondARM32::Cond Cond) {
+                         CondARM32::Cond Cond, const TargetInfo &TInfo) {
   IValueT Rt;
   if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Address;
-  if (decodeAddress(OpAddress, Address) != DecodedAsImmRegOffset)
+  if (decodeAddress(OpAddress, Address, TInfo) != DecodedAsImmRegOffset)
     return setNeedsTextFixup();
   // STR (immediate) - ARM section A8.8.204, encoding A1:
   //   str<c> <Rt>, [<Rn>{, #+/-<imm12>}]      ; p=1, w=0
   //   str<c> <Rt>, [<Rn>], #+/-<imm12>        ; p=1, w=1
   //   str<c> <Rt>, [<Rn>, #+/-<imm12>]!       ; p=0, w=1
   // STRB (immediate) - ARM section A8.8.207, encoding A1:
   //   strb<c> <Rt>, [<Rn>{, #+/-<imm12>}]     ; p=1, w=0
   //   strb<c> <Rt>, [<Rn>], #+/-<imm12>       ; p=1, w=1
   //   strb<c> <Rt>, [<Rn>, #+/-<imm12>]!      ; p=0, w=1
   //
@@ skipping 225 matching lines @@
   if (RdHi == RegARM32::Encoded_Reg_pc || RdLo == RegARM32::Encoded_Reg_pc ||
       Rn == RegARM32::Encoded_Reg_pc || Rm == RegARM32::Encoded_Reg_pc ||
       RdHi == RdLo)
     llvm::report_fatal_error("Umull instruction unpredictable on pc");
   constexpr bool SetFlags = false;
   emitMulOp(Cond, B23, RdLo, RdHi, Rn, Rm, SetFlags);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice