Fix frame pointer loads/stores in the ARM integrated assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 41 matching lines @@
 public:
   MoveRelocatableFixup() = default;
   size_t emit(GlobalContext *Ctx, const Assembler &Asm) const override;
 };
 
 class AssemblerARM32 : public Assembler {
   AssemblerARM32(const AssemblerARM32 &) = delete;
   AssemblerARM32 &operator=(const AssemblerARM32 &) = delete;
 
 public:
+  class TargetInfo {
+    TargetInfo(const TargetInfo &) = delete;
+    TargetInfo &operator=(const TargetInfo &) = delete;
+
+  public:
+    TargetInfo(bool HasFramePointer, SizeT FrameOrStackReg,
+               int32_t StackAdjustment)
+        : HasFramePointer(HasFramePointer), FrameOrStackReg(FrameOrStackReg),
+          StackAdjustment(StackAdjustment) {}
+    explicit TargetInfo(const TargetLowering *Target)
+        : HasFramePointer(Target->hasFramePointer()),
+          FrameOrStackReg(Target->getFrameOrStackReg()),
+          StackAdjustment(Target->getStackAdjustment()) {}
+    const bool HasFramePointer;
+    const SizeT FrameOrStackReg;
+    const int32_t StackAdjustment;
+  };
+
   explicit AssemblerARM32(bool use_far_branches = false)
       : Assembler(Asm_ARM32) {
     // TODO(kschimpf): Add mode if needed when branches are handled.
     (void)use_far_branches;
   }
   ~AssemblerARM32() override {
     if (BuildDefs::asserts()) {
       for (const Label *Label : CfgNodeLabels) {
         Label->finalCheck();
       }
@@ skipping 93 matching lines @@
   void bkpt(uint16_t Imm16);
 
   void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
 
   void bic(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void eor(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
-  void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
+  void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
+           const TargetInfo &Target);
+
+  void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
+           const TargetLowering *Lowering) {
+    TargetInfo Target(Lowering);
+    ldr(OpRt, OpAddress, Cond, Target);
+  }
 
   void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
 
   void movw(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
 
   void movt(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
 
   void mla(const Operand *OpRd, const Operand *OpRn, const Operand *OpRm,
            const Operand *OpRa, CondARM32::Cond Cond);
 
   void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void push(const Operand *OpRt, CondARM32::Cond Cond);
 
   // Note: Registers is a bitset, where bit n corresponds to register Rn.
   void pushList(const IValueT Registers, CondARM32::Cond Cond);
 
   void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void sdiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
             CondARM32::Cond Cond);
 
-  void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
+  void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
+           const TargetInfo &Target);
+
+  void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
+           const TargetLowering *Lowering) {
+    TargetInfo Target(Lowering);
+    str(OpRt, OpAddress, Cond, Target);
+  }
 
   void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void tst(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
 
   void udiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
             CondARM32::Cond Cond);
 
   void umull(const Operand *OpRdLo, const Operand *OpRdHi, const Operand *OpRn,
@@ skipping 94 matching lines @@
   IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst);
 
   // Returns the offset encoded in the branch instruction Inst.
   static IOffsetT decodeBranchOffset(IValueT Inst);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H