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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1372 vsd(0x2c, idst, xmm0, src, kF2, k0F, kW0); | 1372 vsd(0x2c, idst, xmm0, src, kF2, k0F, kW0); |
1373 } | 1373 } |
1374 void vcvttsd2siq(Register dst, XMMRegister src) { | 1374 void vcvttsd2siq(Register dst, XMMRegister src) { |
1375 XMMRegister idst = {dst.code()}; | 1375 XMMRegister idst = {dst.code()}; |
1376 vsd(0x2c, idst, xmm0, src, kF2, k0F, kW1); | 1376 vsd(0x2c, idst, xmm0, src, kF2, k0F, kW1); |
1377 } | 1377 } |
1378 void vcvttsd2siq(Register dst, const Operand& src) { | 1378 void vcvttsd2siq(Register dst, const Operand& src) { |
1379 XMMRegister idst = {dst.code()}; | 1379 XMMRegister idst = {dst.code()}; |
1380 vsd(0x2c, idst, xmm0, src, kF2, k0F, kW1); | 1380 vsd(0x2c, idst, xmm0, src, kF2, k0F, kW1); |
1381 } | 1381 } |
| 1382 void vcvtsd2si(Register dst, XMMRegister src) { |
| 1383 XMMRegister idst = {dst.code()}; |
| 1384 vsd(0x2d, idst, xmm0, src, kF2, k0F, kW0); |
| 1385 } |
1382 void vucomisd(XMMRegister dst, XMMRegister src) { | 1386 void vucomisd(XMMRegister dst, XMMRegister src) { |
1383 vsd(0x2e, dst, xmm0, src, k66, k0F, kWIG); | 1387 vsd(0x2e, dst, xmm0, src, k66, k0F, kWIG); |
1384 } | 1388 } |
1385 void vucomisd(XMMRegister dst, const Operand& src) { | 1389 void vucomisd(XMMRegister dst, const Operand& src) { |
1386 vsd(0x2e, dst, xmm0, src, k66, k0F, kWIG); | 1390 vsd(0x2e, dst, xmm0, src, k66, k0F, kWIG); |
1387 } | 1391 } |
1388 void vroundsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, | 1392 void vroundsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, |
1389 RoundingMode mode) { | 1393 RoundingMode mode) { |
1390 vsd(0x0b, dst, src1, src2, k66, k0F3A, kWIG); | 1394 vsd(0x0b, dst, src1, src2, k66, k0F3A, kWIG); |
1391 emit(static_cast<byte>(mode) | 0x8); // Mask precision exception. | 1395 emit(static_cast<byte>(mode) | 0x8); // Mask precision exception. |
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2154 Assembler* assembler_; | 2158 Assembler* assembler_; |
2155 #ifdef DEBUG | 2159 #ifdef DEBUG |
2156 int space_before_; | 2160 int space_before_; |
2157 #endif | 2161 #endif |
2158 }; | 2162 }; |
2159 | 2163 |
2160 } // namespace internal | 2164 } // namespace internal |
2161 } // namespace v8 | 2165 } // namespace v8 |
2162 | 2166 |
2163 #endif // V8_X64_ASSEMBLER_X64_H_ | 2167 #endif // V8_X64_ASSEMBLER_X64_H_ |
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