Implemented the Word64Clz TurboFan operator for x64, arm64, and mips64.

src/mips64/disasm-mips64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 1161 matching lines @@
       } else {
         if ((instr->FunctionFieldRaw() == CLZ_R6) && (instr->FdValue() == 1)) {
           Format(instr, "clz     'rd, 'rs");
         } else if ((instr->FunctionFieldRaw() == CLO_R6) &&
                    (instr->FdValue() == 1)) {
           Format(instr, "clo     'rd, 'rs");
         }
       }
       break;
     case MFLO:
-      Format(instr, "mflo    'rd");
+      if (instr->Bits(25, 16) == 0) {
+        Format(instr, "mflo    'rd");
+      } else {
+        if ((instr->FunctionFieldRaw() == DCLZ_R6) && (instr->FdValue() == 1)) {
+          Format(instr, "dclz    'rd, 'rs");
+        } else if ((instr->FunctionFieldRaw() == DCLO_R6) &&
+                   (instr->FdValue() == 1)) {
+          Format(instr, "dclo     'rd, 'rs");
+        }
+      }
       break;
     case D_MUL_MUH_U:  // Equals to DMULTU.
       if (kArchVariant != kMips64r6) {
         Format(instr, "dmultu  'rs, 'rt");
       } else {
         if (instr->SaValue() == MUL_OP) {
           Format(instr, "dmulu  'rd, 'rs, 'rt");
         } else {
           Format(instr, "dmuhu  'rd, 'rs, 'rt");
         }
@@ skipping 160 matching lines @@
 void Decoder::DecodeTypeRegisterSPECIAL2(Instruction* instr) {
   switch (instr->FunctionFieldRaw()) {
     case MUL:
       Format(instr, "mul     'rd, 'rs, 'rt");
       break;
     case CLZ:
       if (kArchVariant != kMips64r6) {
         Format(instr, "clz     'rd, 'rs");
       }
       break;
+    case DCLZ:
+      if (kArchVariant != kMips64r6) {
+        Format(instr, "dclz    'rd, 'rs");
+      }
+      break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Decoder::DecodeTypeRegisterSPECIAL3(Instruction* instr) {
   switch (instr->FunctionFieldRaw()) {
     case INS: {
       Format(instr, "ins     'rt, 'rs, 'sa, 'ss2");
@@ skipping 552 matching lines @@
         prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 #undef UNSUPPORTED
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_MIPS64