Implemented the Word64Clz TurboFan operator for x64, arm64, and mips64.

src/mips64/constants-mips64.h

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef  V8_MIPS_CONSTANTS_H_
 #define  V8_MIPS_CONSTANTS_H_
 
 #include "src/base/logging.h"
 #include "src/base/macros.h"
 #include "src/globals.h"
@@ skipping 376 matching lines @@
   JR = ((1 << 3) + 0),
   JALR = ((1 << 3) + 1),
   MOVZ = ((1 << 3) + 2),
   MOVN = ((1 << 3) + 3),
   BREAK = ((1 << 3) + 5),
 
   MFHI = ((2 << 3) + 0),
   CLZ_R6 = ((2 << 3) + 0),
   CLO_R6 = ((2 << 3) + 1),
   MFLO = ((2 << 3) + 2),
+  DCLZ_R6 = ((2 << 3) + 2),
+  DCLO_R6 = ((2 << 3) + 3),
   DSLLV = ((2 << 3) + 4),
   DSRLV = ((2 << 3) + 6),
   DSRAV = ((2 << 3) + 7),
 
   MULT = ((3 << 3) + 0),
   MULTU = ((3 << 3) + 1),
   DIV = ((3 << 3) + 2),
   DIVU = ((3 << 3) + 3),
   DMULT = ((3 << 3) + 4),
   DMULTU = ((3 << 3) + 5),
@@ skipping 48 matching lines @@
   DIV_MOD_U = ((3 << 3) + 3),
   D_DIV_MOD = ((3 << 3) + 6),
   D_DIV_MOD_U = ((3 << 3) + 7),
 
   // drotr in special4?
 
   // SPECIAL2 Encoding of Function Field.
   MUL = ((0 << 3) + 2),
   CLZ = ((4 << 3) + 0),
   CLO = ((4 << 3) + 1),
+  DCLZ = ((4 << 3) + 4),
+  DCLO = ((4 << 3) + 5),
 
   // SPECIAL3 Encoding of Function Field.
   EXT = ((0 << 3) + 0),
   DEXTM = ((0 << 3) + 1),
   DEXTU = ((0 << 3) + 2),
   DEXT = ((0 << 3) + 3),
   INS = ((0 << 3) + 4),
   DINSM = ((0 << 3) + 5),
   DINSU = ((0 << 3) + 6),
   DINS = ((0 << 3) + 7),
@@ skipping 445 matching lines @@
       OpcodeToBitNumber(LD) | OpcodeToBitNumber(LBU) | OpcodeToBitNumber(LHU) |
       OpcodeToBitNumber(LWR) | OpcodeToBitNumber(SB) | OpcodeToBitNumber(SH) |
       OpcodeToBitNumber(SWL) | OpcodeToBitNumber(SW) | OpcodeToBitNumber(SD) |
       OpcodeToBitNumber(SWR) | OpcodeToBitNumber(LWC1) |
       OpcodeToBitNumber(LDC1) | OpcodeToBitNumber(SWC1) |
       OpcodeToBitNumber(SDC1) | OpcodeToBitNumber(PCREL) |
       OpcodeToBitNumber(BC) | OpcodeToBitNumber(BALC);
 
 #define FunctionFieldToBitNumber(function) (1ULL << function)
 
+  // On r6, DCLZ_R6 aliases to existing MFLO.
   static const uint64_t kFunctionFieldRegisterTypeMask =
       FunctionFieldToBitNumber(JR) | FunctionFieldToBitNumber(JALR) |
       FunctionFieldToBitNumber(BREAK) | FunctionFieldToBitNumber(SLL) |
       FunctionFieldToBitNumber(DSLL) | FunctionFieldToBitNumber(DSLL32) |
       FunctionFieldToBitNumber(SRL) | FunctionFieldToBitNumber(DSRL) |
       FunctionFieldToBitNumber(DSRL32) | FunctionFieldToBitNumber(SRA) |
       FunctionFieldToBitNumber(DSRA) | FunctionFieldToBitNumber(DSRA32) |
       FunctionFieldToBitNumber(SLLV) | FunctionFieldToBitNumber(DSLLV) |
       FunctionFieldToBitNumber(SRLV) | FunctionFieldToBitNumber(DSRLV) |
       FunctionFieldToBitNumber(SRAV) | FunctionFieldToBitNumber(DSRAV) |
@@ skipping 224 matching lines @@
           return kUnsupported;
         }
       } else {
         return kRegisterType;
       }
       break;
     case SPECIAL2:
       switch (FunctionFieldRaw()) {
         case MUL:
         case CLZ:
+        case DCLZ:
           return kRegisterType;
         default:
           return kUnsupported;
       }
       break;
     case SPECIAL3:
       switch (FunctionFieldRaw()) {
         case INS:
         case EXT:
         case DEXT:
@@ skipping 65 matching lines @@
   }
   return kUnsupported;
 }
 
 #undef OpcodeToBitNumber
 #undef FunctionFieldToBitNumber
 }  // namespace internal
 }  // namespace v8
 
 #endif    // #ifndef V8_MIPS_CONSTANTS_H_