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1 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===// | 1 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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962 class InstARM32Push : public InstARM32 { | 962 class InstARM32Push : public InstARM32 { |
963 InstARM32Push() = delete; | 963 InstARM32Push() = delete; |
964 InstARM32Push(const InstARM32Push &) = delete; | 964 InstARM32Push(const InstARM32Push &) = delete; |
965 InstARM32Push &operator=(const InstARM32Push &) = delete; | 965 InstARM32Push &operator=(const InstARM32Push &) = delete; |
966 | 966 |
967 public: | 967 public: |
968 static InstARM32Push *create(Cfg *Func, const VarList &Srcs) { | 968 static InstARM32Push *create(Cfg *Func, const VarList &Srcs) { |
969 return new (Func->allocate<InstARM32Push>()) InstARM32Push(Func, Srcs); | 969 return new (Func->allocate<InstARM32Push>()) InstARM32Push(Func, Srcs); |
970 } | 970 } |
971 void emit(const Cfg *Func) const override; | 971 void emit(const Cfg *Func) const override; |
| 972 void emitIAS(const Cfg *Func) const override; |
972 void dump(const Cfg *Func) const override; | 973 void dump(const Cfg *Func) const override; |
973 static bool classof(const Inst *Inst) { return isClassof(Inst, Push); } | 974 static bool classof(const Inst *Inst) { return isClassof(Inst, Push); } |
974 | 975 |
975 private: | 976 private: |
976 InstARM32Push(Cfg *Func, const VarList &Srcs); | 977 InstARM32Push(Cfg *Func, const VarList &Srcs); |
977 }; | 978 }; |
978 | 979 |
979 /// Ret pseudo-instruction. This is actually a "bx" instruction with an "lr" | 980 /// Ret pseudo-instruction. This is actually a "bx" instruction with an "lr" |
980 /// register operand, but epilogue lowering will search for a Ret instead of a | 981 /// register operand, but epilogue lowering will search for a Ret instead of a |
981 /// generic "bx". This instruction also takes a Source operand (for non-void | 982 /// generic "bx". This instruction also takes a Source operand (for non-void |
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1242 // default implementations. Without this, there is the possibility of ODR | 1243 // default implementations. Without this, there is the possibility of ODR |
1243 // violations and link errors. | 1244 // violations and link errors. |
1244 | 1245 |
1245 template <> void InstARM32Ldr::emit(const Cfg *Func) const; | 1246 template <> void InstARM32Ldr::emit(const Cfg *Func) const; |
1246 template <> void InstARM32Movw::emit(const Cfg *Func) const; | 1247 template <> void InstARM32Movw::emit(const Cfg *Func) const; |
1247 template <> void InstARM32Movt::emit(const Cfg *Func) const; | 1248 template <> void InstARM32Movt::emit(const Cfg *Func) const; |
1248 | 1249 |
1249 } // end of namespace Ice | 1250 } // end of namespace Ice |
1250 | 1251 |
1251 #endif // SUBZERO_SRC_ICEINSTARM32_H | 1252 #endif // SUBZERO_SRC_ICEINSTARM32_H |
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