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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// | 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// |
2 // | 2 // |
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
4 // for details. All rights reserved. Use of this source code is governed by a | 4 // for details. All rights reserved. Use of this source code is governed by a |
5 // BSD-style license that can be found in the LICENSE file. | 5 // BSD-style license that can be found in the LICENSE file. |
6 // | 6 // |
7 // Modified by the Subzero authors. | 7 // Modified by the Subzero authors. |
8 // | 8 // |
9 //===----------------------------------------------------------------------===// | 9 //===----------------------------------------------------------------------===// |
10 // | 10 // |
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182 | 182 |
183 void mla(const Operand *OpRd, const Operand *OpRn, const Operand *OpRm, | 183 void mla(const Operand *OpRd, const Operand *OpRn, const Operand *OpRm, |
184 const Operand *OpRa, CondARM32::Cond Cond); | 184 const Operand *OpRa, CondARM32::Cond Cond); |
185 | 185 |
186 void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, | 186 void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
187 bool SetFlags, CondARM32::Cond Cond); | 187 bool SetFlags, CondARM32::Cond Cond); |
188 | 188 |
189 void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, | 189 void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
190 bool SetFlags, CondARM32::Cond Cond); | 190 bool SetFlags, CondARM32::Cond Cond); |
191 | 191 |
| 192 void push(const Operand *OpRt, CondARM32::Cond Cond); |
| 193 |
| 194 // Note: Registers is a bitset, where bit n corresponds to register Rn. |
| 195 void pushList(const IValueT Registers, CondARM32::Cond Cond); |
| 196 |
192 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, | 197 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
193 bool SetFlags, CondARM32::Cond Cond); | 198 bool SetFlags, CondARM32::Cond Cond); |
194 | 199 |
195 void sdiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, | 200 void sdiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
196 CondARM32::Cond Cond); | 201 CondARM32::Cond Cond); |
197 | 202 |
198 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); | 203 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); |
199 | 204 |
200 void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, | 205 void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
201 bool SetFlags, CondARM32::Cond Cond); | 206 bool SetFlags, CondARM32::Cond Cond); |
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214 private: | 219 private: |
215 // A vector of pool-allocated x86 labels for CFG nodes. | 220 // A vector of pool-allocated x86 labels for CFG nodes. |
216 using LabelVector = std::vector<Label *>; | 221 using LabelVector = std::vector<Label *>; |
217 LabelVector CfgNodeLabels; | 222 LabelVector CfgNodeLabels; |
218 // A vector of pool-allocated x86 labels for Local labels. | 223 // A vector of pool-allocated x86 labels for Local labels. |
219 LabelVector LocalLabels; | 224 LabelVector LocalLabels; |
220 // Number of bytes emitted by InstARM32::emit() methods, when run inside | 225 // Number of bytes emitted by InstARM32::emit() methods, when run inside |
221 // InstARM32::emitUsingTextFixup(). | 226 // InstARM32::emitUsingTextFixup(). |
222 size_t EmitTextSize = 0; | 227 size_t EmitTextSize = 0; |
223 | 228 |
| 229 // Load/store multiple addressing mode. |
| 230 enum BlockAddressMode { |
| 231 // bit encoding P U W |
| 232 DA = (0 | 0 | 0) << 21, // decrement after |
| 233 IA = (0 | 4 | 0) << 21, // increment after |
| 234 DB = (8 | 0 | 0) << 21, // decrement before |
| 235 IB = (8 | 4 | 0) << 21, // increment before |
| 236 DA_W = (0 | 0 | 1) << 21, // decrement after with writeback to base |
| 237 IA_W = (0 | 4 | 1) << 21, // increment after with writeback to base |
| 238 DB_W = (8 | 0 | 1) << 21, // decrement before with writeback to base |
| 239 IB_W = (8 | 4 | 1) << 21 // increment before with writeback to base |
| 240 }; |
| 241 |
224 Label *getOrCreateLabel(SizeT Number, LabelVector &Labels); | 242 Label *getOrCreateLabel(SizeT Number, LabelVector &Labels); |
225 | 243 |
226 void bindCfgNodeLabel(const CfgNode *Node) override; | 244 void bindCfgNodeLabel(const CfgNode *Node) override; |
227 | 245 |
228 void emitInst(IValueT Value) { Buffer.emit<IValueT>(Value); } | 246 void emitInst(IValueT Value) { Buffer.emit<IValueT>(Value); } |
229 | 247 |
230 // Pattern cccctttoooosnnnnddddiiiiiiiiiiii where cccc=Cond, ttt=Type, | 248 // Pattern cccctttoooosnnnnddddiiiiiiiiiiii where cccc=Cond, ttt=Type, |
231 // oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM section A5.2.3). | 249 // oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM section A5.2.3). |
232 void emitType01(CondARM32::Cond Cond, IValueT Type, IValueT Opcode, | 250 void emitType01(CondARM32::Cond Cond, IValueT Type, IValueT Opcode, |
233 bool SetCc, IValueT Rn, IValueT Rd, IValueT imm12); | 251 bool SetCc, IValueT Rn, IValueT Rd, IValueT imm12); |
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252 | 270 |
253 void emitType05(CondARM32::Cond COnd, int32_t Offset, bool Link); | 271 void emitType05(CondARM32::Cond COnd, int32_t Offset, bool Link); |
254 | 272 |
255 // Pattern ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond, ooo=InstType, | 273 // Pattern ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond, ooo=InstType, |
256 // l=isLoad, b=isByte, and aaa0a0aaaa0000aaaaaaaaaaaa=Address. Note that | 274 // l=isLoad, b=isByte, and aaa0a0aaaa0000aaaaaaaaaaaa=Address. Note that |
257 // Address is assumed to be defined by decodeAddress() in | 275 // Address is assumed to be defined by decodeAddress() in |
258 // IceAssemblerARM32.cpp. | 276 // IceAssemblerARM32.cpp. |
259 void emitMemOp(CondARM32::Cond Cond, IValueT InstType, bool IsLoad, | 277 void emitMemOp(CondARM32::Cond Cond, IValueT InstType, bool IsLoad, |
260 bool IsByte, uint32_t Rt, uint32_t Address); | 278 bool IsByte, uint32_t Rt, uint32_t Address); |
261 | 279 |
| 280 // Pattern cccc100aaaalnnnnrrrrrrrrrrrrrrrr where cccc=Cond, |
| 281 // aaaa<<21=AddressMode, l=IsLoad, nnnn=BaseReg, and |
| 282 // rrrrrrrrrrrrrrrr is bitset of Registers. |
| 283 void emitMultiMemOp(CondARM32::Cond Cond, BlockAddressMode AddressMode, |
| 284 bool IsLoad, IValueT BaseReg, IValueT Registers); |
| 285 |
262 // Pattern cccc011100x1dddd1111mmmm0001nnn where cccc=Cond, | 286 // Pattern cccc011100x1dddd1111mmmm0001nnn where cccc=Cond, |
263 // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm. | 287 // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm. |
264 void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn, | 288 void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn, |
265 IValueT Rm); | 289 IValueT Rm); |
266 | 290 |
267 // Pattern ccccxxxxxxxfnnnnddddssss1001mmmm where cccc=Cond, dddd=Rd, nnnn=Rn, | 291 // Pattern ccccxxxxxxxfnnnnddddssss1001mmmm where cccc=Cond, dddd=Rd, nnnn=Rn, |
268 // mmmm=Rm, ssss=Rs, f=SetCc, and xxxxxxx=Opcode. | 292 // mmmm=Rm, ssss=Rs, f=SetCc, and xxxxxxx=Opcode. |
269 void emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn, | 293 void emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn, |
270 IValueT Rm, IValueT Rs, bool SetCc); | 294 IValueT Rm, IValueT Rs, bool SetCc); |
271 | 295 |
272 // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn, | 296 // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn, |
273 // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from | 297 // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from |
274 // OpSrc1, and xxxx=Opcode. | 298 // OpSrc1, and xxxx=Opcode. |
275 void emitCompareOp(IValueT Opcode, const Operand *OpRn, const Operand *OpSrc1, | 299 void emitCompareOp(IValueT Opcode, const Operand *OpRn, const Operand *OpSrc1, |
276 CondARM32::Cond Cond); | 300 CondARM32::Cond Cond); |
277 | 301 |
278 void emitBranch(Label *L, CondARM32::Cond, bool Link); | 302 void emitBranch(Label *L, CondARM32::Cond, bool Link); |
279 | 303 |
280 // Encodes the given Offset into the branch instruction Inst. | 304 // Encodes the given Offset into the branch instruction Inst. |
281 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst); | 305 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst); |
282 | 306 |
283 // Returns the offset encoded in the branch instruction Inst. | 307 // Returns the offset encoded in the branch instruction Inst. |
284 static IOffsetT decodeBranchOffset(IValueT Inst); | 308 static IOffsetT decodeBranchOffset(IValueT Inst); |
285 }; | 309 }; |
286 | 310 |
287 } // end of namespace ARM32 | 311 } // end of namespace ARM32 |
288 } // end of namespace Ice | 312 } // end of namespace Ice |
289 | 313 |
290 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H | 314 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H |
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