Add orr (register) and orr (immediate) to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 424 matching lines @@
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataRegister, Adc, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   case DecodedAsRotatedImm8: {
     // ADC (Immediate) - ARM section A8.8.1, encoding A1:
     //   adc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
     //
     // cccc0010101snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
-    // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+    // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
     if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataImmediate, Adc, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   };
 }
 
 void AssemblerARM32::add(const Operand *OpRd, const Operand *OpRn,
@@ skipping 27 matching lines @@
     emitType01(Cond, kInstTypeDataRegister, Add, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   case DecodedAsRotatedImm8: {
     // ADD (Immediate) - ARM section A8.8.5, encoding A1:
     //   add{s}<c> <Rd>, <Rn>, #<RotatedImm8>
     // ADD (SP plus immediate) - ARM section A8.8.9, encoding A1.
     //   add{s}<c> <Rd>, sp, #<RotatedImm8>
     //
     // cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
-    // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+    // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
     if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataImmediate, Add, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   }
 }
 
 void AssemblerARM32::and_(const Operand *OpRd, const Operand *OpRn,
@@ skipping 211 matching lines @@
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataRegister, Sbc, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   case DecodedAsRotatedImm8: {
     // SBC (Immediate) - ARM section A8.8.161, encoding A1:
     //   sbc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
     //
     // cccc0010110snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
-    // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+    // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
     if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataImmediate, Sbc, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   };
 }
 
 void AssemblerARM32::str(const Operand *OpRt, const Operand *OpAddress,
@@ skipping 25 matching lines @@
     return setNeedsTextFixup();
   if (!isBitSet(P, Address) && isBitSet(W, Address))
     return setNeedsTextFixup();
   if (!IsByte && (getGPRReg(kRnShift, Address) == RegARM32::Encoded_Reg_sp) &&
       isBitSet(P, Address) && !isBitSet(U, Address) && isBitSet(W, Address) &&
       (mask(Address, kImm12Shift, kImmed12Bits) == 0x8 /* 000000000100 */))
     return setNeedsTextFixup();
   emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address);
 }
 
+void AssemblerARM32::orr(const Operand *OpRd, const Operand *OpRn,
+                         const Operand *OpSrc1, bool SetFlags,
+                         CondARM32::Cond Cond) {
+  IValueT Rd;
+  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  IValueT Rn;
+  if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  constexpr IValueT Orr = B3 | B2; // i.e. 1100
+  IValueT Src1Value;
+  // TODO(kschimpf) Handle other possible decodings of orr.
+  switch (decodeOperand(OpSrc1, Src1Value)) {
+  default:
+    return setNeedsTextFixup();
+  case DecodedAsRegister: {
+    // ORR (register) - ARM Section A8.8.123, encoding A1:
+    //   orr{s}<c> <Rd>, <Rn>, <Rm>
+    //
+    // cccc0001100snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
+    // mmmm=Rm, iiiii=shift, tt=ShiftKind,, and s=SetFlags.
+    constexpr IValueT Shift = 0;
+    Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Shift);
+    if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
+      // Conditions of rule violated.
+      return setNeedsTextFixup();
+    emitType01(Cond, kInstTypeDataRegister, Orr, SetFlags, Rn, Rd, Src1Value);
+    return;
+  }
+  case DecodedAsRotatedImm8: {
+    // ORR (register) - ARM Section A8.8.123, encoding A1:
+    //   orr{s}<c> <Rd>, <Rn>,  #<RotatedImm8>
+    //
+    // cccc0001100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
+    // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
+    if (Rd == RegARM32::Encoded_Reg_pc && SetFlags)
+      // Conditions of rule violated.
+      return setNeedsTextFixup();
+    emitType01(Cond, kInstTypeDataImmediate, Orr, SetFlags, Rn, Rd, Src1Value);
+    return;
+  }
+  }
+}
+
 void AssemblerARM32::mul(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   IValueT Rd;
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
   if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rm;
@@ skipping 28 matching lines @@
   default:
     return setNeedsTextFixup();
   case DecodedAsRegister: {
     // SUB (register) - ARM section A8.8.223, encoding A1:
     //   sub{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
     // SUB (SP minus register): See ARM section 8.8.226, encoding A1:
     //   sub{s}<c> <Rd>, sp, <Rm>{, <Shift>}
     //
     // cccc0000010snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
     // mmmm=Rm, iiiiii=shift, tt=ShiftKind, and s=SetFlags.
-    Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, 0);
+    constexpr IValueT Shift = 0;
+    Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Shift);
     if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataRegister, Sub, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   case DecodedAsRotatedImm8: {
     // Sub (Immediate) - ARM section A8.8.222, encoding A1:
     //    sub{s}<c> <Rd>, <Rn>, #<RotatedImm8>
     // Sub (Sp minus immediate) - ARM section A8.*.225, encoding A1:
     //    sub{s}<c> sp, <Rn>, #<RotatedImm8>
     //
     // cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
-    // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8
+    // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
     if (Rd == RegARM32::Encoded_Reg_pc)
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataImmediate, Sub, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   }
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice