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Side by Side Diff: src/IceAssemblerARM32.h

Issue 1412293006: Add AND(register) and AND(immediate) to ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 1 month ago
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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
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134 void bind(Label *label); 134 void bind(Label *label);
135 135
136 // List of instructions implemented by integrated assembler. 136 // List of instructions implemented by integrated assembler.
137 137
138 void adc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 138 void adc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
139 bool SetFlags, CondARM32::Cond Cond); 139 bool SetFlags, CondARM32::Cond Cond);
140 140
141 void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 141 void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
142 bool SetFlags, CondARM32::Cond Cond); 142 bool SetFlags, CondARM32::Cond Cond);
143 143
144 void and_(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
145 bool SetFlags, CondARM32::Cond Cond);
146
144 void b(Label *L, CondARM32::Cond Cond); 147 void b(Label *L, CondARM32::Cond Cond);
145 148
146 void bkpt(uint16_t Imm16); 149 void bkpt(uint16_t Imm16);
147 150
148 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); 151 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
149 152
150 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); 153 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
151 154
152 void movw(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); 155 void movw(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
153 156
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202 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst); 205 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst);
203 206
204 // Returns the offset encoded in the branch instruction Inst. 207 // Returns the offset encoded in the branch instruction Inst.
205 static IOffsetT decodeBranchOffset(IValueT Inst); 208 static IOffsetT decodeBranchOffset(IValueT Inst);
206 }; 209 };
207 210
208 } // end of namespace ARM32 211 } // end of namespace ARM32
209 } // end of namespace Ice 212 } // end of namespace Ice
210 213
211 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H 214 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H
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