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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 // | 4 // |
| 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
| 6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
| 7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
| 8 | 8 |
| 9 #include "vm/globals.h" // NOLINT | 9 #include "vm/globals.h" // NOLINT |
| 10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
| (...skipping 167 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 178 static_cast<int32_t>(MOV) << kOpcodeShift | | 178 static_cast<int32_t>(MOV) << kOpcodeShift | |
| 179 static_cast<int32_t>(rd) << kRdShift | | 179 static_cast<int32_t>(rd) << kRdShift | |
| 180 o.encoding() << kShiftRegisterShift | | 180 o.encoding() << kShiftRegisterShift | |
| 181 static_cast<int32_t>(opcode) << kShiftShift | | 181 static_cast<int32_t>(opcode) << kShiftShift | |
| 182 B4 | | 182 B4 | |
| 183 static_cast<int32_t>(rm); | 183 static_cast<int32_t>(rm); |
| 184 Emit(encoding); | 184 Emit(encoding); |
| 185 } | 185 } |
| 186 | 186 |
| 187 | 187 |
| 188 #if 0 |
| 189 // Moved to ARM32::AssemblerARM32::and_() |
| 188 void Assembler::and_(Register rd, Register rn, Operand o, Condition cond) { | 190 void Assembler::and_(Register rd, Register rn, Operand o, Condition cond) { |
| 189 EmitType01(cond, o.type(), AND, 0, rn, rd, o); | 191 EmitType01(cond, o.type(), AND, 0, rn, rd, o); |
| 190 } | 192 } |
| 191 | 193 #endif |
| 192 | 194 |
| 193 void Assembler::eor(Register rd, Register rn, Operand o, Condition cond) { | 195 void Assembler::eor(Register rd, Register rn, Operand o, Condition cond) { |
| 194 EmitType01(cond, o.type(), EOR, 0, rn, rd, o); | 196 EmitType01(cond, o.type(), EOR, 0, rn, rd, o); |
| 195 } | 197 } |
| 196 | 198 |
| 197 #if 0 | 199 #if 0 |
| 198 // Moved to ARM32::AssemberARM32::sub() | 200 // Moved to ARM32::AssemberARM32::sub() |
| 199 void Assembler::sub(Register rd, Register rn, Operand o, Condition cond) { | 201 void Assembler::sub(Register rd, Register rn, Operand o, Condition cond) { |
| 200 EmitType01(cond, o.type(), SUB, 0, rn, rd, o); | 202 EmitType01(cond, o.type(), SUB, 0, rn, rd, o); |
| 201 } | 203 } |
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| 3671 | 3673 |
| 3672 | 3674 |
| 3673 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3675 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
| 3674 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3676 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
| 3675 return fpu_reg_names[reg]; | 3677 return fpu_reg_names[reg]; |
| 3676 } | 3678 } |
| 3677 | 3679 |
| 3678 } // namespace dart | 3680 } // namespace dart |
| 3679 | 3681 |
| 3680 #endif // defined TARGET_ARCH_ARM | 3682 #endif // defined TARGET_ARCH_ARM |
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