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Issue 1411873002: emit add/sub registers instructions in integrated ARM assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nits. Created 5 years, 2 months ago
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1 ; Show that we know how to translate add. 1 ; Show that we know how to translate add.
2 ; TODO(kschimpf) Currently only know how to test add 1 to R0.
3 2
4 ; NOTE: We use -O2 to get rid of memory stores. 3 ; NOTE: We use -O2 to get rid of memory stores.
5 4
6 ; REQUIRES: allow_dump 5 ; REQUIRES: allow_dump
7 6
8 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ 7 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
9 ; RUN: | FileCheck %s --check-prefix=ASM 8 ; RUN: | FileCheck %s --check-prefix=ASM
10 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \ 9 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
11 ; RUN: | FileCheck %s --check-prefix=IASM 10 ; RUN: | FileCheck %s --check-prefix=IASM
12 11
13 define internal i32 @add1ToR0(i32 %p) { 12 define internal i32 @add1ToR0(i32 %p) {
14 %v = add i32 %p, 1 13 %v = add i32 %p, 1
15 ret i32 %v 14 ret i32 %v
16 } 15 }
17 16
18 ; ASM-LABEL: add1ToR0: 17 ; ASM-LABEL: add1ToR0:
19 ; ASM: add r0, r0, #1 18 ; ASM: add r0, r0, #1
20 ; ASM: bx lr 19 ; ASM-NEXT: bx lr
21 20
22 ; IASM-LABEL: add1ToR0: 21 ; IASM-LABEL: add1ToR0:
23 ; IASM: .byte 0x1 22 ; IASM: .byte 0x1
24 ; IASM-NEXT: .byte 0x0 23 ; IASM-NEXT: .byte 0x0
25 ; IASM-NEXT: .byte 0x80 24 ; IASM-NEXT: .byte 0x80
26 ; IASM-NEXT: .byte 0xe2 25 ; IASM-NEXT: .byte 0xe2
27 26
27 define internal i32 @Add2Regs(i32 %p1, i32 %p2) {
28 %v = add i32 %p1, %p2
29 ret i32 %v
30 }
31
32 ; ASM-LABEL: Add2Regs:
33 ; ASM: add r0, r0, r1
34 ; ASM-NEXT: bx lr
35
36 ; IASM-LABEL: Add2Regs:
37
38 ; IASM: .byte 0x1
39 ; IASM-NEXT: .byte 0x0
40 ; IASM-NEXT: .byte 0x80
41 ; IASM-NEXT: .byte 0xe0
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