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Unified Diff: src/IceInstX86BaseImpl.h

Issue 1411583007: Combine allocas (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Finish fast path. Created 5 years, 1 month ago
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Index: src/IceInstX86BaseImpl.h
diff --git a/src/IceInstX86BaseImpl.h b/src/IceInstX86BaseImpl.h
index e109bf2a3350cfab526e87ce517f9411ecf908a5..80a1f6bcc4c36e883c674b338481302b8689f4c7 100644
--- a/src/IceInstX86BaseImpl.h
+++ b/src/IceInstX86BaseImpl.h
@@ -569,48 +569,51 @@ void InstX86Call<Machine>::emit(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrEmit();
assert(this->getSrcSize() == 1);
Str << "\tcall\t";
- if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(getCallTarget())) {
+ Operand *CallTarget = getCallTarget();
+ TargetLowering *Target = Func->getTarget();
+ if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(CallTarget)) {
// Emit without a leading '$'.
Str << CI->getValue();
- } else if (const auto CallTarget =
- llvm::dyn_cast<ConstantRelocatable>(getCallTarget())) {
- CallTarget->emitWithoutPrefix(Func->getTarget());
+ } else if (const auto DirectCallTarget =
+ llvm::dyn_cast<ConstantRelocatable>(CallTarget)) {
+ DirectCallTarget->emitWithoutPrefix(Target);
} else {
Str << "*";
- getCallTarget()->emit(Func);
+ CallTarget->emit(Func);
}
- Func->getTarget()->resetStackAdjustment();
+ Target->resetStackAdjustment();
}
template <class Machine>
void InstX86Call<Machine>::emitIAS(const Cfg *Func) const {
typename InstX86Base<Machine>::Traits::Assembler *Asm =
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
- Operand *Target = getCallTarget();
- if (const auto *Var = llvm::dyn_cast<Variable>(Target)) {
+ Operand *CallTarget = getCallTarget();
+ TargetLowering *Target = Func->getTarget();
+ if (const auto *Var = llvm::dyn_cast<Variable>(CallTarget)) {
if (Var->hasReg()) {
Asm->call(InstX86Base<Machine>::Traits::getEncodedGPR(Var->getRegNum()));
} else {
Asm->call(
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(Var));
}
} else if (const auto *Mem = llvm::dyn_cast<
typename InstX86Base<Machine>::Traits::X86OperandMem>(
- Target)) {
+ CallTarget)) {
assert(Mem->getSegmentRegister() ==
InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
- Asm->call(Mem->toAsmAddress(Asm));
- } else if (const auto *CR = llvm::dyn_cast<ConstantRelocatable>(Target)) {
+ Asm->call(Mem->toAsmAddress(Asm, Target));
+ } else if (const auto *CR = llvm::dyn_cast<ConstantRelocatable>(CallTarget)) {
assert(CR->getOffset() == 0 && "We only support calling a function");
Asm->call(CR);
- } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Target)) {
+ } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(CallTarget)) {
Asm->call(Immediate(Imm->getValue()));
} else {
llvm_unreachable("Unexpected operand type");
}
- Func->getTarget()->resetStackAdjustment();
+ Target->resetStackAdjustment();
}
template <class Machine>
@@ -651,6 +654,7 @@ template <class Machine>
void emitIASOpTyGPR(const Cfg *Func, Type Ty, const Operand *Op,
const typename InstX86Base<
Machine>::Traits::Assembler::GPREmitterOneOp &Emitter) {
+ TargetLowering *Target = Func->getTarget();
typename InstX86Base<Machine>::Traits::Assembler *Asm =
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
if (const auto *Var = llvm::dyn_cast<Variable>(Op)) {
@@ -662,14 +666,14 @@ void emitIASOpTyGPR(const Cfg *Func, Type Ty, const Operand *Op,
} else {
typename InstX86Base<Machine>::Traits::Address StackAddr(
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(Var));
(Asm->*(Emitter.Addr))(Ty, StackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<
typename InstX86Base<Machine>::Traits::X86OperandMem>(Op)) {
Mem->emitSegmentOverride(Asm);
- (Asm->*(Emitter.Addr))(Ty, Mem->toAsmAddress(Asm));
+ (Asm->*(Emitter.Addr))(Ty, Mem->toAsmAddress(Asm, Target));
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -680,6 +684,7 @@ void emitIASRegOpTyGPR(
const Cfg *Func, Type Ty, const Variable *Var, const Operand *Src,
const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterRegOp
&Emitter) {
+ TargetLowering *Target = Func->getTarget();
typename InstX86Base<Machine>::Traits::Assembler *Asm =
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
assert(Var->hasReg());
@@ -699,14 +704,14 @@ void emitIASRegOpTyGPR(
} else {
typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(SrcVar);
(Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<
typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
Mem->emitSegmentOverride(Asm);
- (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Mem->toAsmAddress(Asm));
+ (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Mem->toAsmAddress(Asm, Target));
} else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
(Asm->*(Emitter.GPRImm))(Ty, VarReg, Immediate(Imm->getValue()));
} else if (const auto *Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
@@ -752,11 +757,12 @@ void emitIASAsAddrOpTyGPR(
const Cfg *Func, Type Ty, const Operand *Op0, const Operand *Op1,
const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterAddrOp
&Emitter) {
+ TargetLowering *Target = Func->getTarget();
if (const auto *Op0Var = llvm::dyn_cast<Variable>(Op0)) {
assert(!Op0Var->hasReg());
typename InstX86Base<Machine>::Traits::Address StackAddr(
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(Op0Var));
emitIASAddrOpTyGPR<Machine>(Func, Ty, StackAddr, Op1, Emitter);
} else if (const auto *Op0Mem = llvm::dyn_cast<
@@ -764,8 +770,8 @@ void emitIASAsAddrOpTyGPR(
typename InstX86Base<Machine>::Traits::Assembler *Asm =
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
Op0Mem->emitSegmentOverride(Asm);
- emitIASAddrOpTyGPR<Machine>(Func, Ty, Op0Mem->toAsmAddress(Asm), Op1,
- Emitter);
+ emitIASAddrOpTyGPR<Machine>(Func, Ty, Op0Mem->toAsmAddress(Asm, Target),
+ Op1, Emitter);
} else if (const auto *Split = llvm::dyn_cast<
typename InstX86Base<Machine>::Traits::VariableSplit>(Op0)) {
emitIASAddrOpTyGPR<Machine>(Func, Ty, Split->toAsmAddress(Func), Op1,
@@ -835,6 +841,7 @@ void emitIASXmmShift(
const Cfg *Func, Type Ty, const Variable *Var, const Operand *Src,
const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterShiftOp
&Emitter) {
+ TargetLowering *Target = Func->getTarget();
typename InstX86Base<Machine>::Traits::Assembler *Asm =
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
assert(Var->hasReg());
@@ -848,7 +855,7 @@ void emitIASXmmShift(
} else {
typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(SrcVar);
(Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcStackAddr);
}
@@ -856,7 +863,7 @@ void emitIASXmmShift(
typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
assert(Mem->getSegmentRegister() ==
InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
- (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Asm));
+ (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Asm, Target));
} else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
(Asm->*(Emitter.XmmImm))(Ty, VarReg, Immediate(Imm->getValue()));
} else {
@@ -869,6 +876,7 @@ void emitIASRegOpTyXMM(
const Cfg *Func, Type Ty, const Variable *Var, const Operand *Src,
const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterRegOp
&Emitter) {
+ TargetLowering *Target = Func->getTarget();
typename InstX86Base<Machine>::Traits::Assembler *Asm =
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
assert(Var->hasReg());
@@ -882,7 +890,7 @@ void emitIASRegOpTyXMM(
} else {
typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(SrcVar);
(Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcStackAddr);
}
@@ -890,7 +898,7 @@ void emitIASRegOpTyXMM(
typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
assert(Mem->getSegmentRegister() ==
InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
- (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Asm));
+ (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Asm, Target));
} else if (const auto *Imm = llvm::dyn_cast<Constant>(Src)) {
(Asm->*(Emitter.XmmAddr))(
Ty, VarReg,
@@ -906,6 +914,7 @@ void emitIASCastRegOp(const Cfg *Func, Type DestTy, const Variable *Dest,
Type SrcTy, const Operand *Src,
const typename InstX86Base<Machine>::Traits::Assembler::
template CastEmitterRegOp<DReg_t, SReg_t> &Emitter) {
+ TargetLowering *Target = Func->getTarget();
typename InstX86Base<Machine>::Traits::Assembler *Asm =
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
assert(Dest->hasReg());
@@ -917,14 +926,15 @@ void emitIASCastRegOp(const Cfg *Func, Type DestTy, const Variable *Dest,
} else {
typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(SrcVar);
(Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy, SrcStackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<
typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
Mem->emitSegmentOverride(Asm);
- (Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy, Mem->toAsmAddress(Asm));
+ (Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy,
+ Mem->toAsmAddress(Asm, Target));
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -937,6 +947,7 @@ void emitIASThreeOpImmOps(
const Operand *Src1,
const typename InstX86Base<Machine>::Traits::Assembler::
template ThreeOpImmEmitter<DReg_t, SReg_t> Emitter) {
+ TargetLowering *Target = Func->getTarget();
typename InstX86Base<Machine>::Traits::Assembler *Asm =
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
// This only handles Dest being a register, and Src1 being an immediate.
@@ -950,15 +961,15 @@ void emitIASThreeOpImmOps(
} else {
typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(SrcVar);
(Asm->*(Emitter.RegAddrImm))(DispatchTy, DestReg, SrcStackAddr, Imm);
}
} else if (const auto *Mem = llvm::dyn_cast<
typename InstX86Base<Machine>::Traits::X86OperandMem>(Src0)) {
Mem->emitSegmentOverride(Asm);
- (Asm->*(Emitter.RegAddrImm))(DispatchTy, DestReg, Mem->toAsmAddress(Asm),
- Imm);
+ (Asm->*(Emitter.RegAddrImm))(DispatchTy, DestReg,
+ Mem->toAsmAddress(Asm, Target), Imm);
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -969,6 +980,7 @@ void emitIASMovlikeXMM(
const Cfg *Func, const Variable *Dest, const Operand *Src,
const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterMovOps
Emitter) {
+ TargetLowering *Target = Func->getTarget();
typename InstX86Base<Machine>::Traits::Assembler *Asm =
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
if (Dest->hasReg()) {
@@ -981,8 +993,8 @@ void emitIASMovlikeXMM(
InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()));
} else {
typename InstX86Base<Machine>::Traits::Address StackAddr(
- static_cast<typename InstX86Base<Machine>::Traits::TargetLowering
- *>(Func->getTarget())
+ static_cast<
+ typename InstX86Base<Machine>::Traits::TargetLowering *>(Target)
->stackVarToAsmOperand(SrcVar));
(Asm->*(Emitter.XmmAddr))(DestReg, StackAddr);
}
@@ -990,14 +1002,14 @@ void emitIASMovlikeXMM(
typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
assert(SrcMem->getSegmentRegister() ==
InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
- (Asm->*(Emitter.XmmAddr))(DestReg, SrcMem->toAsmAddress(Asm));
+ (Asm->*(Emitter.XmmAddr))(DestReg, SrcMem->toAsmAddress(Asm, Target));
} else {
llvm_unreachable("Unexpected operand type");
}
} else {
typename InstX86Base<Machine>::Traits::Address StackAddr(
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(Dest));
// Src must be a register in this case.
const auto *SrcVar = llvm::cast<Variable>(Src);
@@ -1054,10 +1066,11 @@ void InstX86Pmull<Machine>::emit(const Cfg *Func) const {
char buf[30];
bool TypesAreValid = this->getDest()->getType() == IceType_v4i32 ||
this->getDest()->getType() == IceType_v8i16;
+ TargetLowering *Target = Func->getTarget();
bool InstructionSetIsValid =
this->getDest()->getType() == IceType_v8i16 ||
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1;
(void)TypesAreValid;
(void)InstructionSetIsValid;
@@ -1074,10 +1087,11 @@ template <class Machine>
void InstX86Pmull<Machine>::emitIAS(const Cfg *Func) const {
Type Ty = this->getDest()->getType();
bool TypesAreValid = Ty == IceType_v4i32 || Ty == IceType_v8i16;
+ TargetLowering *Target = Func->getTarget();
bool InstructionSetIsValid =
Ty == IceType_v8i16 ||
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1;
(void)TypesAreValid;
(void)InstructionSetIsValid;
@@ -1222,16 +1236,18 @@ template <class Machine>
void InstX86Blendvps<Machine>::emit(const Cfg *Func) const {
if (!BuildDefs::dump())
return;
+ TargetLowering *Target = Func->getTarget();
assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
emitVariableBlendInst<Machine>(this->Opcode, this, Func);
}
template <class Machine>
void InstX86Blendvps<Machine>::emitIAS(const Cfg *Func) const {
+ TargetLowering *Target = Func->getTarget();
assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
static const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterRegOp
Emitter = {&InstX86Base<Machine>::Traits::Assembler::blendvps,
@@ -1243,16 +1259,18 @@ template <class Machine>
void InstX86Pblendvb<Machine>::emit(const Cfg *Func) const {
if (!BuildDefs::dump())
return;
+ TargetLowering *Target = Func->getTarget();
assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
emitVariableBlendInst<Machine>(this->Opcode, this, Func);
}
template <class Machine>
void InstX86Pblendvb<Machine>::emitIAS(const Cfg *Func) const {
+ TargetLowering *Target = Func->getTarget();
assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
static const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterRegOp
Emitter = {&InstX86Base<Machine>::Traits::Assembler::pblendvb,
@@ -1357,8 +1375,9 @@ void InstX86ImulImm<Machine>::emitIAS(const Cfg *Func) const {
template <class Machine>
void InstX86Insertps<Machine>::emitIAS(const Cfg *Func) const {
assert(this->getSrcSize() == 3);
+ TargetLowering *Target = Func->getTarget();
assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
const Variable *Dest = this->getDest();
assert(Dest == this->getSrc(0));
@@ -1605,6 +1624,7 @@ void InstX86Cmov<Machine>::emitIAS(const Cfg *Func) const {
(InstX86Base<Machine>::Traits::Is64Bit));
typename InstX86Base<Machine>::Traits::Assembler *Asm =
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
+ TargetLowering *Target = Func->getTarget();
if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
if (SrcVar->hasReg()) {
Asm->cmov(
@@ -1616,7 +1636,7 @@ void InstX86Cmov<Machine>::emitIAS(const Cfg *Func) const {
SrcTy, Condition, InstX86Base<Machine>::Traits::getEncodedGPR(
this->getDest()->getRegNum()),
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(SrcVar));
}
} else if (const auto *Mem = llvm::dyn_cast<
@@ -1625,7 +1645,7 @@ void InstX86Cmov<Machine>::emitIAS(const Cfg *Func) const {
InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
Asm->cmov(SrcTy, Condition, InstX86Base<Machine>::Traits::getEncodedGPR(
this->getDest()->getRegNum()),
- Mem->toAsmAddress(Asm));
+ Mem->toAsmAddress(Asm, Target));
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -1671,6 +1691,7 @@ void InstX86Cmpps<Machine>::emitIAS(const Cfg *Func) const {
// Assuming there isn't any load folding for cmpps, and vector constants are
// not allowed in PNaCl.
assert(llvm::isa<Variable>(this->getSrc(1)));
+ TargetLowering *Target = Func->getTarget();
const auto *SrcVar = llvm::cast<Variable>(this->getSrc(1));
if (SrcVar->hasReg()) {
Asm->cmpps(InstX86Base<Machine>::Traits::getEncodedXmm(
@@ -1680,7 +1701,7 @@ void InstX86Cmpps<Machine>::emitIAS(const Cfg *Func) const {
} else {
typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(SrcVar);
Asm->cmpps(InstX86Base<Machine>::Traits::getEncodedXmm(
this->getDest()->getRegNum()),
@@ -1724,13 +1745,14 @@ void InstX86Cmpxchg<Machine>::emitIAS(const Cfg *Func) const {
typename InstX86Base<Machine>::Traits::Assembler *Asm =
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
Type Ty = this->getSrc(0)->getType();
+ TargetLowering *Target = Func->getTarget();
const auto Mem =
llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
this->getSrc(0));
assert(Mem->getSegmentRegister() ==
InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
const typename InstX86Base<Machine>::Traits::Address Addr =
- Mem->toAsmAddress(Asm);
+ Mem->toAsmAddress(Asm, Target);
const auto *VarReg = llvm::cast<Variable>(this->getSrc(2));
assert(VarReg->hasReg());
const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg =
@@ -1773,8 +1795,9 @@ void InstX86Cmpxchg8b<Machine>::emitIAS(const Cfg *Func) const {
this->getSrc(0));
assert(Mem->getSegmentRegister() ==
InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
+ TargetLowering *Target = Func->getTarget();
const typename InstX86Base<Machine>::Traits::Address Addr =
- Mem->toAsmAddress(Asm);
+ Mem->toAsmAddress(Asm, Target);
Asm->cmpxchg8b(Addr, this->Locked);
}
@@ -2114,11 +2137,12 @@ void InstX86Store<Machine>::emitIAS(const Cfg *Func) const {
InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum());
typename InstX86Base<Machine>::Traits::Assembler *Asm =
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
+ TargetLowering *Target = Func->getTarget();
if (const auto *DestVar = llvm::dyn_cast<Variable>(Dest)) {
assert(!DestVar->hasReg());
typename InstX86Base<Machine>::Traits::Address StackAddr(
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(DestVar));
Asm->movss(DestTy, StackAddr, SrcReg);
} else {
@@ -2127,7 +2151,7 @@ void InstX86Store<Machine>::emitIAS(const Cfg *Func) const {
Dest);
assert(DestMem->getSegmentRegister() ==
InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
- Asm->movss(DestTy, DestMem->toAsmAddress(Asm), SrcReg);
+ Asm->movss(DestTy, DestMem->toAsmAddress(Asm, Target), SrcReg);
}
return;
} else {
@@ -2176,7 +2200,8 @@ void InstX86StoreP<Machine>::emitIAS(const Cfg *Func) const {
assert(DestMem->getSegmentRegister() ==
InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
assert(SrcVar->hasReg());
- Asm->movups(DestMem->toAsmAddress(Asm),
+ TargetLowering *Target = Func->getTarget();
+ Asm->movups(DestMem->toAsmAddress(Asm, Target),
InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()));
}
@@ -2218,7 +2243,8 @@ void InstX86StoreQ<Machine>::emitIAS(const Cfg *Func) const {
assert(DestMem->getSegmentRegister() ==
InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
assert(SrcVar->hasReg());
- Asm->movq(DestMem->toAsmAddress(Asm),
+ TargetLowering *Target = Func->getTarget();
+ Asm->movq(DestMem->toAsmAddress(Asm, Target),
InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()));
}
@@ -2281,8 +2307,9 @@ template <class Machine> void InstX86Mov<Machine>::emit(const Cfg *Func) const {
// TODO: This assert disallows usages such as copying a floating
// point value between a vector and a scalar (which movss is used for). Clean
// this up.
- assert(Func->getTarget()->typeWidthInBytesOnStack(DestTy) ==
- Func->getTarget()->typeWidthInBytesOnStack(SrcTy));
+ TargetLowering *Target = Func->getTarget();
+ assert(Target->typeWidthInBytesOnStack(DestTy) ==
+ Target->typeWidthInBytesOnStack(SrcTy));
const Operand *NewSrc = Src;
if (auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
int32_t NewRegNum = Variable::NoRegister;
@@ -2326,9 +2353,9 @@ void InstX86Mov<Machine>::emitIAS(const Cfg *Func) const {
// TODO: This assert disallows usages such as copying a floating
// point value between a vector and a scalar (which movss is used for). Clean
// this up.
- assert(
- Func->getTarget()->typeWidthInBytesOnStack(this->getDest()->getType()) ==
- Func->getTarget()->typeWidthInBytesOnStack(Src->getType()));
+ TargetLowering *Target = Func->getTarget();
+ assert(Target->typeWidthInBytesOnStack(this->getDest()->getType()) ==
+ Target->typeWidthInBytesOnStack(Src->getType()));
if (Dest->hasReg()) {
if (isScalarFloatingType(DestTy)) {
emitIASRegOpTyXMM<Machine>(Func, DestTy, Dest, Src, XmmRegEmitter);
@@ -2362,7 +2389,7 @@ void InstX86Mov<Machine>::emitIAS(const Cfg *Func) const {
// decide on the emitters.
typename InstX86Base<Machine>::Traits::Address StackAddr(
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(Dest));
if (isScalarFloatingType(SrcTy)) {
// Src must be a register.
@@ -2391,6 +2418,7 @@ void InstX86Movd<Machine>::emitIAS(const Cfg *Func) const {
assert(this->getSrcSize() == 1);
const Variable *Dest = this->getDest();
const auto *SrcVar = llvm::cast<Variable>(this->getSrc(0));
+ TargetLowering *Target = Func->getTarget();
// For insert/extract element (one of Src/Dest is an Xmm vector and the other
// is an int type).
if (SrcVar->getType() == IceType_i32 ||
@@ -2410,7 +2438,7 @@ void InstX86Movd<Machine>::emitIAS(const Cfg *Func) const {
} else {
typename InstX86Base<Machine>::Traits::Address StackAddr(
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(SrcVar));
Asm->movd(SrcVar->getType(), DestReg, StackAddr);
}
@@ -2432,7 +2460,7 @@ void InstX86Movd<Machine>::emitIAS(const Cfg *Func) const {
} else {
typename InstX86Base<Machine>::Traits::Address StackAddr(
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(Dest));
Asm->movd(Dest->getType(), StackAddr, SrcReg);
}
@@ -2595,6 +2623,7 @@ void InstX86Fld<Machine>::emitIAS(const Cfg *Func) const {
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
assert(this->getSrcSize() == 1);
const Operand *Src = this->getSrc(0);
+ TargetLowering *Target = Func->getTarget();
Type Ty = Src->getType();
if (const auto *Var = llvm::dyn_cast<Variable>(Src)) {
if (Var->hasReg()) {
@@ -2617,7 +2646,7 @@ void InstX86Fld<Machine>::emitIAS(const Cfg *Func) const {
} else {
typename InstX86Base<Machine>::Traits::Address StackAddr(
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(Var));
Asm->fld(Ty, StackAddr);
}
@@ -2625,7 +2654,7 @@ void InstX86Fld<Machine>::emitIAS(const Cfg *Func) const {
typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
assert(Mem->getSegmentRegister() ==
InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
- Asm->fld(Ty, Mem->toAsmAddress(Asm));
+ Asm->fld(Ty, Mem->toAsmAddress(Asm, Target));
} else if (const auto *Imm = llvm::dyn_cast<Constant>(Src)) {
Asm->fld(Ty, InstX86Base<Machine>::Traits::Address::ofConstPool(Asm, Imm));
} else {
@@ -2688,11 +2717,12 @@ void InstX86Fstp<Machine>::emitIAS(const Cfg *Func) const {
Asm->fstp(InstX86Base<Machine>::Traits::RegisterSet::getEncodedSTReg(0));
return;
}
+ TargetLowering *Target = Func->getTarget();
Type Ty = Dest->getType();
if (!Dest->hasReg()) {
typename InstX86Base<Machine>::Traits::Address StackAddr(
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(Dest));
Asm->fstp(Ty, StackAddr);
} else {
@@ -2755,10 +2785,11 @@ void InstX86Pextr<Machine>::emit(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrEmit();
assert(this->getSrcSize() == 2);
// pextrb and pextrd are SSE4.1 instructions.
+ TargetLowering *Target = Func->getTarget();
assert(this->getSrc(0)->getType() == IceType_v8i16 ||
this->getSrc(0)->getType() == IceType_v8i1 ||
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
Str << "\t" << this->Opcode
<< InstX86Base<Machine>::Traits::TypeAttributes[this->getSrc(0)
@@ -2783,9 +2814,10 @@ void InstX86Pextr<Machine>::emitIAS(const Cfg *Func) const {
const Variable *Dest = this->getDest();
Type DispatchTy = InstX86Base<Machine>::Traits::getInVectorElementType(
this->getSrc(0)->getType());
+ TargetLowering *Target = Func->getTarget();
assert(DispatchTy == IceType_i16 ||
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
// pextrw must take a register dest. There is an SSE4.1 version that takes a
// memory dest, but we aren't using it. For uniformity, just restrict them
@@ -2813,10 +2845,11 @@ void InstX86Pinsr<Machine>::emit(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrEmit();
assert(this->getSrcSize() == 3);
// pinsrb and pinsrd are SSE4.1 instructions.
+ TargetLowering *Target = Func->getTarget();
assert(this->getDest()->getType() == IceType_v8i16 ||
this->getDest()->getType() == IceType_v8i1 ||
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
Str << "\t" << this->Opcode
<< InstX86Base<
@@ -2849,9 +2882,10 @@ void InstX86Pinsr<Machine>::emitIAS(const Cfg *Func) const {
// pinsrb and pinsrd are SSE4.1 instructions.
const Operand *Src0 = this->getSrc(1);
Type DispatchTy = Src0->getType();
+ TargetLowering *Target = Func->getTarget();
assert(DispatchTy == IceType_i16 ||
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
// If src1 is a register, it should always be r32 (this should fall out from
// the encodings for ByteRegs overlapping the encodings for r32), but we have
@@ -2939,9 +2973,10 @@ void InstX86Pop<Machine>::emitIAS(const Cfg *Func) const {
Asm->popl(InstX86Base<Machine>::Traits::getEncodedGPR(
this->getDest()->getRegNum()));
} else {
+ TargetLowering *Target = Func->getTarget();
Asm->popl(
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(this->getDest()));
}
}
@@ -2960,7 +2995,8 @@ void InstX86AdjustStack<Machine>::emit(const Cfg *Func) const {
return;
Ostream &Str = Func->getContext()->getStrEmit();
Str << "\tsubl\t$" << Amount << ", %esp";
- Func->getTarget()->updateStackAdjustment(Amount);
+ TargetLowering *Target = Func->getTarget();
+ Target->updateStackAdjustment(Amount);
}
template <class Machine>
@@ -2970,7 +3006,8 @@ void InstX86AdjustStack<Machine>::emitIAS(const Cfg *Func) const {
Asm->sub(IceType_i32,
InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp,
Immediate(Amount));
- Func->getTarget()->updateStackAdjustment(Amount);
+ TargetLowering *Target = Func->getTarget();
+ Target->updateStackAdjustment(Amount);
}
template <class Machine>
@@ -3100,6 +3137,7 @@ void InstX86Setcc<Machine>::emitIAS(const Cfg *Func) const {
assert(this->getSrcSize() == 0);
typename InstX86Base<Machine>::Traits::Assembler *Asm =
Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
+ TargetLowering *Target = Func->getTarget();
if (this->getDest()->hasReg())
Asm->setcc(Condition, InstX86Base<Machine>::Traits::getEncodedByteReg(
this->getDest()->getRegNum()));
@@ -3107,7 +3145,7 @@ void InstX86Setcc<Machine>::emitIAS(const Cfg *Func) const {
Asm->setcc(
Condition,
static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
- Func->getTarget())
+ Target)
->stackVarToAsmOperand(this->getDest()));
return;
}
@@ -3148,8 +3186,9 @@ void InstX86Xadd<Machine>::emitIAS(const Cfg *Func) const {
this->getSrc(0));
assert(Mem->getSegmentRegister() ==
InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
+ TargetLowering *Target = Func->getTarget();
const typename InstX86Base<Machine>::Traits::Address Addr =
- Mem->toAsmAddress(Asm);
+ Mem->toAsmAddress(Asm, Target);
const auto *VarReg = llvm::cast<Variable>(this->getSrc(1));
assert(VarReg->hasReg());
const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg =
@@ -3205,8 +3244,9 @@ void InstX86Xchg<Machine>::emitIAS(const Cfg *Func) const {
this->getSrc(0));
assert(Mem->getSegmentRegister() ==
InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
+ TargetLowering *Target = Func->getTarget();
const typename InstX86Base<Machine>::Traits::Address Addr =
- Mem->toAsmAddress(Asm);
+ Mem->toAsmAddress(Asm, Target);
Asm->xchg(Ty, Addr, Reg1);
}
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