Combine allocas

src/IceInstX86BaseImpl.h

 //===- subzero/src/IceInstX86BaseImpl.h - Generic X86 instructions -*- C++ -*=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 551 matching lines @@
   getJmpTarget()->dump(Func);
 }
 
 template <class Machine>
 void InstX86Call<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   Str << "\tcall\t";
-  if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(getCallTarget())) {
+  Operand *CallTarget = getCallTarget();
+  TargetLowering *Target = Func->getTarget();
+  if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(CallTarget)) {
     // Emit without a leading '$'.
     Str << CI->getValue();
-  } else if (const auto CallTarget =
-                 llvm::dyn_cast<ConstantRelocatable>(getCallTarget())) {
-    CallTarget->emitWithoutPrefix(Func->getTarget());
+  } else if (const auto DirectCallTarget =
+                 llvm::dyn_cast<ConstantRelocatable>(CallTarget)) {
+    DirectCallTarget->emitWithoutPrefix(Target);
   } else {
     Str << "*";
-    getCallTarget()->emit(Func);
+    CallTarget->emit(Func);
   }
-  Func->getTarget()->resetStackAdjustment();
+  Target->resetStackAdjustment();
 }
 
 template <class Machine>
 void InstX86Call<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
-  Operand *Target = getCallTarget();
-  if (const auto *Var = llvm::dyn_cast<Variable>(Target)) {
+  Operand *CallTarget = getCallTarget();
+  TargetLowering *Target = Func->getTarget();
+  if (const auto *Var = llvm::dyn_cast<Variable>(CallTarget)) {
     if (Var->hasReg()) {
       Asm->call(InstX86Base<Machine>::Traits::getEncodedGPR(Var->getRegNum()));
     } else {
       Asm->call(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-              Func->getTarget())
+              Target)
               ->stackVarToAsmOperand(Var));
     }
   } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(
-                 Target)) {
+                 CallTarget)) {
     assert(Mem->getSegmentRegister() ==
            InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
-    Asm->call(Mem->toAsmAddress(Asm));
-  } else if (const auto *CR = llvm::dyn_cast<ConstantRelocatable>(Target)) {
+    Asm->call(Mem->toAsmAddress(Asm, Target));
+  } else if (const auto *CR = llvm::dyn_cast<ConstantRelocatable>(CallTarget)) {
     assert(CR->getOffset() == 0 && "We only support calling a function");
     Asm->call(CR);
-  } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Target)) {
+  } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(CallTarget)) {
     Asm->call(Immediate(Imm->getValue()));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
-  Func->getTarget()->resetStackAdjustment();
+  Target->resetStackAdjustment();
 }
 
 template <class Machine>
 void InstX86Call<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   if (this->getDest()) {
     this->dumpDest(Func);
     Str << " = ";
@@ skipping 20 matching lines @@
       << "\t";
   Src1->emit(Func);
   Str << ", ";
   Dest->emit(Func);
 }
 
 template <class Machine>
 void emitIASOpTyGPR(const Cfg *Func, Type Ty, const Operand *Op,
                     const typename InstX86Base<
                         Machine>::Traits::Assembler::GPREmitterOneOp &Emitter) {
+  TargetLowering *Target = Func->getTarget();
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   if (const auto *Var = llvm::dyn_cast<Variable>(Op)) {
     if (Var->hasReg()) {
       // We cheat a little and use GPRRegister even for byte operations.
       typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister VarReg =
           InstX86Base<Machine>::Traits::getEncodedGPR(Var->getRegNum());
       (Asm->*(Emitter.Reg))(Ty, VarReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address StackAddr(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-              Func->getTarget())
+              Target)
               ->stackVarToAsmOperand(Var));
       (Asm->*(Emitter.Addr))(Ty, StackAddr);
     }
   } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Op)) {
     Mem->emitSegmentOverride(Asm);
-    (Asm->*(Emitter.Addr))(Ty, Mem->toAsmAddress(Asm));
+    (Asm->*(Emitter.Addr))(Ty, Mem->toAsmAddress(Asm, Target));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine, bool VarCanBeByte, bool SrcCanBeByte>
 void emitIASRegOpTyGPR(
     const Cfg *Func, Type Ty, const Variable *Var, const Operand *Src,
     const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterRegOp
         &Emitter) {
+  TargetLowering *Target = Func->getTarget();
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(Var->hasReg());
   // We cheat a little and use GPRRegister even for byte operations.
   typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister VarReg =
       VarCanBeByte
           ? InstX86Base<Machine>::Traits::getEncodedGPR(Var->getRegNum())
           : InstX86Base<Machine>::Traits::getEncodedGPR(Var->getRegNum());
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
       typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister SrcReg =
           SrcCanBeByte
               ? InstX86Base<Machine>::Traits::getEncodedGPR(SrcVar->getRegNum())
               : InstX86Base<Machine>::Traits::getEncodedGPR(
                     SrcVar->getRegNum());
       (Asm->*(Emitter.GPRGPR))(Ty, VarReg, SrcReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-              Func->getTarget())
+              Target)
               ->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr);
     }
   } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     Mem->emitSegmentOverride(Asm);
-    (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Mem->toAsmAddress(Asm));
+    (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Mem->toAsmAddress(Asm, Target));
   } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, Immediate(Imm->getValue()));
   } else if (const auto *Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
     AssemblerFixup *Fixup =
         Asm->createFixup(InstX86Base<Machine>::Traits::RelFixup, Reloc);
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, Immediate(Reloc->getOffset(), Fixup));
   } else if (const auto *Split = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::VariableSplit>(Src)) {
     (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Split->toAsmAddress(Func));
   } else {
@@ skipping 25 matching lines @@
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void emitIASAsAddrOpTyGPR(
     const Cfg *Func, Type Ty, const Operand *Op0, const Operand *Op1,
     const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterAddrOp
         &Emitter) {
+  TargetLowering *Target = Func->getTarget();
   if (const auto *Op0Var = llvm::dyn_cast<Variable>(Op0)) {
     assert(!Op0Var->hasReg());
     typename InstX86Base<Machine>::Traits::Address StackAddr(
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-            Func->getTarget())
+            Target)
             ->stackVarToAsmOperand(Op0Var));
     emitIASAddrOpTyGPR<Machine>(Func, Ty, StackAddr, Op1, Emitter);
   } else if (const auto *Op0Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Op0)) {
     typename InstX86Base<Machine>::Traits::Assembler *Asm =
         Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
     Op0Mem->emitSegmentOverride(Asm);
-    emitIASAddrOpTyGPR<Machine>(Func, Ty, Op0Mem->toAsmAddress(Asm), Op1,
-                                Emitter);
+    emitIASAddrOpTyGPR<Machine>(Func, Ty, Op0Mem->toAsmAddress(Asm, Target),
+                                Op1, Emitter);
   } else if (const auto *Split = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::VariableSplit>(Op0)) {
     emitIASAddrOpTyGPR<Machine>(Func, Ty, Split->toAsmAddress(Func), Op1,
                                 Emitter);
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
@@ skipping 49 matching lines @@
            InstX86Base<Machine>::Traits::RegisterSet::Reg_cl);
     (Asm->*(Emitter.GPRGPR))(Ty, DestReg, SrcReg);
   }
 }
 
 template <class Machine>
 void emitIASXmmShift(
     const Cfg *Func, Type Ty, const Variable *Var, const Operand *Src,
     const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterShiftOp
         &Emitter) {
+  TargetLowering *Target = Func->getTarget();
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(Var->hasReg());
   typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister VarReg =
       InstX86Base<Machine>::Traits::getEncodedXmm(Var->getRegNum());
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
       typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister SrcReg =
           InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum());
       (Asm->*(Emitter.XmmXmm))(Ty, VarReg, SrcReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-              Func->getTarget())
+              Target)
               ->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcStackAddr);
     }
   } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     assert(Mem->getSegmentRegister() ==
            InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
-    (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Asm));
+    (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Asm, Target));
   } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.XmmImm))(Ty, VarReg, Immediate(Imm->getValue()));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void emitIASRegOpTyXMM(
     const Cfg *Func, Type Ty, const Variable *Var, const Operand *Src,
     const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterRegOp
         &Emitter) {
+  TargetLowering *Target = Func->getTarget();
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(Var->hasReg());
   typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister VarReg =
       InstX86Base<Machine>::Traits::getEncodedXmm(Var->getRegNum());
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
       typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister SrcReg =
           InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum());
       (Asm->*(Emitter.XmmXmm))(Ty, VarReg, SrcReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-              Func->getTarget())
+              Target)
               ->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcStackAddr);
     }
   } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     assert(Mem->getSegmentRegister() ==
            InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
-    (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Asm));
+    (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Asm, Target));
   } else if (const auto *Imm = llvm::dyn_cast<Constant>(Src)) {
     (Asm->*(Emitter.XmmAddr))(
         Ty, VarReg,
         InstX86Base<Machine>::Traits::Address::ofConstPool(Asm, Imm));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine, typename DReg_t, typename SReg_t,
           DReg_t (*destEnc)(int32_t), SReg_t (*srcEnc)(int32_t)>
 void emitIASCastRegOp(const Cfg *Func, Type DestTy, const Variable *Dest,
                       Type SrcTy, const Operand *Src,
                       const typename InstX86Base<Machine>::Traits::Assembler::
                           template CastEmitterRegOp<DReg_t, SReg_t> &Emitter) {
+  TargetLowering *Target = Func->getTarget();
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(Dest->hasReg());
   DReg_t DestReg = destEnc(Dest->getRegNum());
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
       SReg_t SrcReg = srcEnc(SrcVar->getRegNum());
       (Asm->*(Emitter.RegReg))(DestTy, DestReg, SrcTy, SrcReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-              Func->getTarget())
+              Target)
               ->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy, SrcStackAddr);
     }
   } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     Mem->emitSegmentOverride(Asm);
-    (Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy, Mem->toAsmAddress(Asm));
+    (Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy,
+                              Mem->toAsmAddress(Asm, Target));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine, typename DReg_t, typename SReg_t,
           DReg_t (*destEnc)(int32_t), SReg_t (*srcEnc)(int32_t)>
 void emitIASThreeOpImmOps(
     const Cfg *Func, Type DispatchTy, const Variable *Dest, const Operand *Src0,
     const Operand *Src1,
     const typename InstX86Base<Machine>::Traits::Assembler::
         template ThreeOpImmEmitter<DReg_t, SReg_t> Emitter) {
+  TargetLowering *Target = Func->getTarget();
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   // This only handles Dest being a register, and Src1 being an immediate.
   assert(Dest->hasReg());
   DReg_t DestReg = destEnc(Dest->getRegNum());
   Immediate Imm(llvm::cast<ConstantInteger32>(Src1)->getValue());
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src0)) {
     if (SrcVar->hasReg()) {
       SReg_t SrcReg = srcEnc(SrcVar->getRegNum());
       (Asm->*(Emitter.RegRegImm))(DispatchTy, DestReg, SrcReg, Imm);
     } else {
       typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-              Func->getTarget())
+              Target)
               ->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.RegAddrImm))(DispatchTy, DestReg, SrcStackAddr, Imm);
     }
   } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src0)) {
     Mem->emitSegmentOverride(Asm);
-    (Asm->*(Emitter.RegAddrImm))(DispatchTy, DestReg, Mem->toAsmAddress(Asm),
-                                 Imm);
+    (Asm->*(Emitter.RegAddrImm))(DispatchTy, DestReg,
+                                 Mem->toAsmAddress(Asm, Target), Imm);
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void emitIASMovlikeXMM(
     const Cfg *Func, const Variable *Dest, const Operand *Src,
     const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterMovOps
         Emitter) {
+  TargetLowering *Target = Func->getTarget();
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   if (Dest->hasReg()) {
     typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister DestReg =
         InstX86Base<Machine>::Traits::getEncodedXmm(Dest->getRegNum());
     if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
       if (SrcVar->hasReg()) {
         (Asm->*(Emitter.XmmXmm))(
             DestReg,
             InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()));
       } else {
         typename InstX86Base<Machine>::Traits::Address StackAddr(
-            static_cast<typename InstX86Base<Machine>::Traits::TargetLowering
-                            *>(Func->getTarget())
+            static_cast<
+                typename InstX86Base<Machine>::Traits::TargetLowering *>(Target)
                 ->stackVarToAsmOperand(SrcVar));
         (Asm->*(Emitter.XmmAddr))(DestReg, StackAddr);
       }
     } else if (const auto *SrcMem = llvm::dyn_cast<
                    typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
       assert(SrcMem->getSegmentRegister() ==
              InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
-      (Asm->*(Emitter.XmmAddr))(DestReg, SrcMem->toAsmAddress(Asm));
+      (Asm->*(Emitter.XmmAddr))(DestReg, SrcMem->toAsmAddress(Asm, Target));
     } else {
       llvm_unreachable("Unexpected operand type");
     }
   } else {
     typename InstX86Base<Machine>::Traits::Address StackAddr(
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-            Func->getTarget())
+            Target)
             ->stackVarToAsmOperand(Dest));
     // Src must be a register in this case.
     const auto *SrcVar = llvm::cast<Variable>(Src);
     assert(SrcVar->hasReg());
     (Asm->*(Emitter.AddrXmm))(
         StackAddr,
         InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()));
   }
 }
 
@@ skipping 36 matching lines @@
   this->emitTwoAddress(buf, this, Func);
 }
 
 template <class Machine>
 void InstX86Pmull<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   char buf[30];
   bool TypesAreValid = this->getDest()->getType() == IceType_v4i32 ||
                        this->getDest()->getType() == IceType_v8i16;
+  TargetLowering *Target = Func->getTarget();
   bool InstructionSetIsValid =
       this->getDest()->getType() == IceType_v8i16 ||
       static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-          Func->getTarget())
+          Target)
               ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1;
   (void)TypesAreValid;
   (void)InstructionSetIsValid;
   assert(TypesAreValid);
   assert(InstructionSetIsValid);
   snprintf(
       buf, llvm::array_lengthof(buf), "pmull%s",
       InstX86Base<Machine>::Traits::TypeAttributes[this->getDest()->getType()]
           .PackString);
   this->emitTwoAddress(buf, this, Func);
 }
 
 template <class Machine>
 void InstX86Pmull<Machine>::emitIAS(const Cfg *Func) const {
   Type Ty = this->getDest()->getType();
   bool TypesAreValid = Ty == IceType_v4i32 || Ty == IceType_v8i16;
+  TargetLowering *Target = Func->getTarget();
   bool InstructionSetIsValid =
       Ty == IceType_v8i16 ||
       static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-          Func->getTarget())
+          Target)
               ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1;
   (void)TypesAreValid;
   (void)InstructionSetIsValid;
   assert(TypesAreValid);
   assert(InstructionSetIsValid);
   assert(this->getSrcSize() == 2);
   Type ElementTy = typeElementType(Ty);
   emitIASRegOpTyXMM<Machine>(Func, ElementTy, this->getDest(), this->getSrc(1),
                              this->Emitter);
 }
@@ skipping 124 matching lines @@
          InstX86Base<Machine>::Traits::RegisterSet::Reg_xmm0);
   const Variable *Dest = Inst->getDest();
   const Operand *Src = Inst->getSrc(1);
   emitIASRegOpTyXMM<Machine>(Func, Dest->getType(), Dest, Src, Emitter);
 }
 
 template <class Machine>
 void InstX86Blendvps<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
+  TargetLowering *Target = Func->getTarget();
   assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-             Func->getTarget())
+             Target)
              ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   emitVariableBlendInst<Machine>(this->Opcode, this, Func);
 }
 
 template <class Machine>
 void InstX86Blendvps<Machine>::emitIAS(const Cfg *Func) const {
+  TargetLowering *Target = Func->getTarget();
   assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-             Func->getTarget())
+             Target)
              ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   static const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterRegOp
       Emitter = {&InstX86Base<Machine>::Traits::Assembler::blendvps,
                  &InstX86Base<Machine>::Traits::Assembler::blendvps};
   emitIASVariableBlendInst<Machine>(this, Func, Emitter);
 }
 
 template <class Machine>
 void InstX86Pblendvb<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
+  TargetLowering *Target = Func->getTarget();
   assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-             Func->getTarget())
+             Target)
              ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   emitVariableBlendInst<Machine>(this->Opcode, this, Func);
 }
 
 template <class Machine>
 void InstX86Pblendvb<Machine>::emitIAS(const Cfg *Func) const {
+  TargetLowering *Target = Func->getTarget();
   assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-             Func->getTarget())
+             Target)
              ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   static const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterRegOp
       Emitter = {&InstX86Base<Machine>::Traits::Assembler::pblendvb,
                  &InstX86Base<Machine>::Traits::Assembler::pblendvb};
   emitIASVariableBlendInst<Machine>(this, Func, Emitter);
 }
 
 template <class Machine>
 void InstX86Imul<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
@@ skipping 84 matching lines @@
       Machine, typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
       typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
       InstX86Base<Machine>::Traits::getEncodedGPR,
       InstX86Base<Machine>::Traits::getEncodedGPR>(
       Func, Ty, Dest, this->getSrc(0), this->getSrc(1), Emitter);
 }
 
 template <class Machine>
 void InstX86Insertps<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 3);
+  TargetLowering *Target = Func->getTarget();
   assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-             Func->getTarget())
+             Target)
              ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   const Variable *Dest = this->getDest();
   assert(Dest == this->getSrc(0));
   Type Ty = Dest->getType();
   static const typename InstX86Base<Machine>::Traits::Assembler::
       template ThreeOpImmEmitter<
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister>
           Emitter = {&InstX86Base<Machine>::Traits::Assembler::insertps,
                      &InstX86Base<Machine>::Traits::Assembler::insertps};
@@ skipping 226 matching lines @@
 void InstX86Cmov<Machine>::emitIAS(const Cfg *Func) const {
   assert(Condition != InstX86Base<Machine>::Traits::Cond::Br_None);
   assert(this->getDest()->hasReg());
   assert(this->getSrcSize() == 2);
   Operand *Src = this->getSrc(1);
   Type SrcTy = Src->getType();
   assert(SrcTy == IceType_i16 || SrcTy == IceType_i32 ||
          (InstX86Base<Machine>::Traits::Is64Bit));
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
+  TargetLowering *Target = Func->getTarget();
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
       Asm->cmov(
           SrcTy, Condition, InstX86Base<Machine>::Traits::getEncodedGPR(
                                 this->getDest()->getRegNum()),
           InstX86Base<Machine>::Traits::getEncodedGPR(SrcVar->getRegNum()));
     } else {
       Asm->cmov(
           SrcTy, Condition, InstX86Base<Machine>::Traits::getEncodedGPR(
                                 this->getDest()->getRegNum()),
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-              Func->getTarget())
+              Target)
               ->stackVarToAsmOperand(SrcVar));
     }
   } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     assert(Mem->getSegmentRegister() ==
            InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
     Asm->cmov(SrcTy, Condition, InstX86Base<Machine>::Traits::getEncodedGPR(
                                     this->getDest()->getRegNum()),
-              Mem->toAsmAddress(Asm));
+              Mem->toAsmAddress(Asm, Target));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void InstX86Cmov<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
@@ skipping 25 matching lines @@
 
 template <class Machine>
 void InstX86Cmpps<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 2);
   assert(Condition < InstX86Base<Machine>::Traits::Cond::Cmpps_Invalid);
   // Assuming there isn't any load folding for cmpps, and vector constants are
   // not allowed in PNaCl.
   assert(llvm::isa<Variable>(this->getSrc(1)));
+  TargetLowering *Target = Func->getTarget();
   const auto *SrcVar = llvm::cast<Variable>(this->getSrc(1));
   if (SrcVar->hasReg()) {
     Asm->cmpps(InstX86Base<Machine>::Traits::getEncodedXmm(
                    this->getDest()->getRegNum()),
                InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()),
                Condition);
   } else {
     typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-            Func->getTarget())
+            Target)
             ->stackVarToAsmOperand(SrcVar);
     Asm->cmpps(InstX86Base<Machine>::Traits::getEncodedXmm(
                    this->getDest()->getRegNum()),
                SrcStackAddr, Condition);
   }
 }
 
 template <class Machine>
 void InstX86Cmpps<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
@@ skipping 23 matching lines @@
   Str << ", ";
   this->getSrc(0)->emit(Func);
 }
 
 template <class Machine>
 void InstX86Cmpxchg<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 3);
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   Type Ty = this->getSrc(0)->getType();
+  TargetLowering *Target = Func->getTarget();
   const auto Mem =
       llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
           this->getSrc(0));
   assert(Mem->getSegmentRegister() ==
          InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
   const typename InstX86Base<Machine>::Traits::Address Addr =
-      Mem->toAsmAddress(Asm);
+      Mem->toAsmAddress(Asm, Target);
   const auto *VarReg = llvm::cast<Variable>(this->getSrc(2));
   assert(VarReg->hasReg());
   const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg =
       InstX86Base<Machine>::Traits::getEncodedGPR(VarReg->getRegNum());
   Asm->cmpxchg(Ty, Addr, Reg, this->Locked);
 }
 
 template <class Machine>
 void InstX86Cmpxchg<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
@@ skipping 22 matching lines @@
 template <class Machine>
 void InstX86Cmpxchg8b<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 5);
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   const auto Mem =
       llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
           this->getSrc(0));
   assert(Mem->getSegmentRegister() ==
          InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
+  TargetLowering *Target = Func->getTarget();
   const typename InstX86Base<Machine>::Traits::Address Addr =
-      Mem->toAsmAddress(Asm);
+      Mem->toAsmAddress(Asm, Target);
   Asm->cmpxchg8b(Addr, this->Locked);
 }
 
 template <class Machine>
 void InstX86Cmpxchg8b<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   if (this->Locked) {
     Str << "lock ";
@@ skipping 319 matching lines @@
   const Operand *Src = this->getSrc(0);
   Type DestTy = Dest->getType();
   if (isScalarFloatingType(DestTy)) {
     // Src must be a register, since Dest is a Mem operand of some kind.
     const auto *SrcVar = llvm::cast<Variable>(Src);
     assert(SrcVar->hasReg());
     typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister SrcReg =
         InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum());
     typename InstX86Base<Machine>::Traits::Assembler *Asm =
         Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
+    TargetLowering *Target = Func->getTarget();
     if (const auto *DestVar = llvm::dyn_cast<Variable>(Dest)) {
       assert(!DestVar->hasReg());
       typename InstX86Base<Machine>::Traits::Address StackAddr(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-              Func->getTarget())
+              Target)
               ->stackVarToAsmOperand(DestVar));
       Asm->movss(DestTy, StackAddr, SrcReg);
     } else {
       const auto DestMem =
           llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
               Dest);
       assert(DestMem->getSegmentRegister() ==
              InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
-      Asm->movss(DestTy, DestMem->toAsmAddress(Asm), SrcReg);
+      Asm->movss(DestTy, DestMem->toAsmAddress(Asm, Target), SrcReg);
     }
     return;
   } else {
     assert(isScalarIntegerType(DestTy));
     static const typename InstX86Base<
         Machine>::Traits::Assembler::GPREmitterAddrOp GPRAddrEmitter = {
         &InstX86Base<Machine>::Traits::Assembler::mov,
         &InstX86Base<Machine>::Traits::Assembler::mov};
     emitIASAsAddrOpTyGPR<Machine>(Func, DestTy, Dest, Src, GPRAddrEmitter);
   }
@@ skipping 28 matching lines @@
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 2);
   const auto *SrcVar = llvm::cast<Variable>(this->getSrc(0));
   const auto DestMem =
       llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
           this->getSrc(1));
   assert(DestMem->getSegmentRegister() ==
          InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
   assert(SrcVar->hasReg());
-  Asm->movups(DestMem->toAsmAddress(Asm),
+  TargetLowering *Target = Func->getTarget();
+  Asm->movups(DestMem->toAsmAddress(Asm, Target),
               InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()));
 }
 
 template <class Machine>
 void InstX86StoreP<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "storep." << this->getSrc(0)->getType() << " ";
   this->getSrc(1)->dump(Func);
@@ skipping 21 matching lines @@
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 2);
   const auto *SrcVar = llvm::cast<Variable>(this->getSrc(0));
   const auto DestMem =
       llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
           this->getSrc(1));
   assert(DestMem->getSegmentRegister() ==
          InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
   assert(SrcVar->hasReg());
-  Asm->movq(DestMem->toAsmAddress(Asm),
+  TargetLowering *Target = Func->getTarget();
+  Asm->movq(DestMem->toAsmAddress(Asm, Target),
             InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum()));
 }
 
 template <class Machine>
 void InstX86StoreQ<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "storeq." << this->getSrc(0)->getType() << " ";
   this->getSrc(1)->dump(Func);
@@ skipping 42 matching lines @@
         << (!isScalarFloatingType(DestTy)
                 ? this->getWidthString(DestTy)
                 : InstX86Base<Machine>::Traits::TypeAttributes[DestTy]
                       .SdSsString) << "\t";
   }
   // For an integer truncation operation, src is wider than dest. In this case,
   // we use a mov instruction whose data width matches the narrower dest.
   // TODO: This assert disallows usages such as copying a floating
   // point value between a vector and a scalar (which movss is used for). Clean
   // this up.
-  assert(Func->getTarget()->typeWidthInBytesOnStack(DestTy) ==
-         Func->getTarget()->typeWidthInBytesOnStack(SrcTy));
+  TargetLowering *Target = Func->getTarget();
+  assert(Target->typeWidthInBytesOnStack(DestTy) ==
+         Target->typeWidthInBytesOnStack(SrcTy));
   const Operand *NewSrc = Src;
   if (auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     int32_t NewRegNum = Variable::NoRegister;
     if (SrcVar->hasReg())
       NewRegNum = InstX86Base<Machine>::Traits::getGprForType(
           DestTy, SrcVar->getRegNum());
     if (SrcTy != DestTy)
       NewSrc = SrcVar->asType(DestTy, NewRegNum);
   }
   NewSrc->emit(Func);
@@ skipping 23 matching lines @@
                        &InstX86Base<Machine>::Traits::Assembler::mov};
   static const typename InstX86Base<
       Machine>::Traits::Assembler::GPREmitterAddrOp GPRAddrEmitter = {
       &InstX86Base<Machine>::Traits::Assembler::mov,
       &InstX86Base<Machine>::Traits::Assembler::mov};
   // For an integer truncation operation, src is wider than dest. In this case,
   // we use a mov instruction whose data width matches the narrower dest.
   // TODO: This assert disallows usages such as copying a floating
   // point value between a vector and a scalar (which movss is used for). Clean
   // this up.
-  assert(
-      Func->getTarget()->typeWidthInBytesOnStack(this->getDest()->getType()) ==
-      Func->getTarget()->typeWidthInBytesOnStack(Src->getType()));
+  TargetLowering *Target = Func->getTarget();
+  assert(Target->typeWidthInBytesOnStack(this->getDest()->getType()) ==
+         Target->typeWidthInBytesOnStack(Src->getType()));
   if (Dest->hasReg()) {
     if (isScalarFloatingType(DestTy)) {
       emitIASRegOpTyXMM<Machine>(Func, DestTy, Dest, Src, XmmRegEmitter);
       return;
     } else {
       assert(isScalarIntegerType(DestTy));
       // Widen DestTy for truncation (see above note). We should only do this
       // when both Src and Dest are integer types.
       if (InstX86Base<Machine>::Traits::Is64Bit && DestTy == IceType_i64 &&
           isIntegerConstant(Src)) {
@@ skipping 13 matching lines @@
         SrcTy = DestTy;
       }
       emitIASRegOpTyGPR<Machine>(Func, DestTy, Dest, Src, GPRRegEmitter);
       return;
     }
   } else {
     // Dest must be Stack and Src *could* be a register. Use Src's type to
     // decide on the emitters.
     typename InstX86Base<Machine>::Traits::Address StackAddr(
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-            Func->getTarget())
+            Target)
             ->stackVarToAsmOperand(Dest));
     if (isScalarFloatingType(SrcTy)) {
       // Src must be a register.
       const auto *SrcVar = llvm::cast<Variable>(Src);
       assert(SrcVar->hasReg());
       typename InstX86Base<Machine>::Traits::Assembler *Asm =
           Func->getAssembler<
               typename InstX86Base<Machine>::Traits::Assembler>();
       Asm->movss(SrcTy, StackAddr, InstX86Base<Machine>::Traits::getEncodedXmm(
                                        SrcVar->getRegNum()));
       return;
     } else {
       // Src can be a register or immediate.
       assert(isScalarIntegerType(SrcTy));
       emitIASAddrOpTyGPR<Machine>(Func, SrcTy, StackAddr, Src, GPRAddrEmitter);
       return;
     }
     return;
   }
 }
 
 template <class Machine>
 void InstX86Movd<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
   const auto *SrcVar = llvm::cast<Variable>(this->getSrc(0));
+  TargetLowering *Target = Func->getTarget();
   // For insert/extract element (one of Src/Dest is an Xmm vector and the other
   // is an int type).
   if (SrcVar->getType() == IceType_i32 ||
       (InstX86Base<Machine>::Traits::Is64Bit &&
        SrcVar->getType() == IceType_i64)) {
     assert(isVectorType(Dest->getType()) ||
            (isScalarFloatingType(Dest->getType()) &&
             typeWidthInBytes(SrcVar->getType()) ==
                 typeWidthInBytes(Dest->getType())));
     assert(Dest->hasReg());
     typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister DestReg =
         InstX86Base<Machine>::Traits::getEncodedXmm(Dest->getRegNum());
     if (SrcVar->hasReg()) {
       Asm->movd(
           SrcVar->getType(), DestReg,
           InstX86Base<Machine>::Traits::getEncodedGPR(SrcVar->getRegNum()));
     } else {
       typename InstX86Base<Machine>::Traits::Address StackAddr(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-              Func->getTarget())
+              Target)
               ->stackVarToAsmOperand(SrcVar));
       Asm->movd(SrcVar->getType(), DestReg, StackAddr);
     }
   } else {
     assert(isVectorType(SrcVar->getType()) ||
            (isScalarFloatingType(SrcVar->getType()) &&
             typeWidthInBytes(SrcVar->getType()) ==
                 typeWidthInBytes(Dest->getType())));
     assert(SrcVar->hasReg());
     assert(Dest->getType() == IceType_i32 ||
            (InstX86Base<Machine>::Traits::Is64Bit &&
             Dest->getType() == IceType_i64));
     typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister SrcReg =
         InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum());
     if (Dest->hasReg()) {
       Asm->movd(Dest->getType(),
                 InstX86Base<Machine>::Traits::getEncodedGPR(Dest->getRegNum()),
                 SrcReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address StackAddr(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-              Func->getTarget())
+              Target)
               ->stackVarToAsmOperand(Dest));
       Asm->movd(Dest->getType(), StackAddr, SrcReg);
     }
   }
 }
 
 template <class Machine>
 void InstX86Movp<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
@@ skipping 142 matching lines @@
   Str << "\tfld" << this->getFldString(Ty) << "\t";
   this->getSrc(0)->emit(Func);
 }
 
 template <class Machine>
 void InstX86Fld<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 1);
   const Operand *Src = this->getSrc(0);
+  TargetLowering *Target = Func->getTarget();
   Type Ty = Src->getType();
   if (const auto *Var = llvm::dyn_cast<Variable>(Src)) {
     if (Var->hasReg()) {
       // This is a physical xmm register, so we need to spill it to a temporary
       // stack slot.
       Immediate Width(typeWidthInBytes(Ty));
       Asm->sub(IceType_i32,
                InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp,
                Width);
       typename InstX86Base<Machine>::Traits::Address StackSlot =
           typename InstX86Base<Machine>::Traits::Address(
               InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp, 0,
               AssemblerFixup::NoFixup);
       Asm->movss(Ty, StackSlot,
                  InstX86Base<Machine>::Traits::getEncodedXmm(Var->getRegNum()));
       Asm->fld(Ty, StackSlot);
       Asm->add(IceType_i32,
                InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp,
                Width);
     } else {
       typename InstX86Base<Machine>::Traits::Address StackAddr(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-              Func->getTarget())
+              Target)
               ->stackVarToAsmOperand(Var));
       Asm->fld(Ty, StackAddr);
     }
   } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     assert(Mem->getSegmentRegister() ==
            InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
-    Asm->fld(Ty, Mem->toAsmAddress(Asm));
+    Asm->fld(Ty, Mem->toAsmAddress(Asm, Target));
   } else if (const auto *Imm = llvm::dyn_cast<Constant>(Src)) {
     Asm->fld(Ty, InstX86Base<Machine>::Traits::Address::ofConstPool(Asm, Imm));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine> void InstX86Fld<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
@@ skipping 42 matching lines @@
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 0);
   const Variable *Dest = this->getDest();
   // TODO(jvoung,stichnot): Utilize this by setting Dest to nullptr to
   // "partially" delete the fstp if the Dest is unused. Even if Dest is unused,
   // the fstp should be kept for the SideEffects of popping the stack.
   if (!Dest) {
     Asm->fstp(InstX86Base<Machine>::Traits::RegisterSet::getEncodedSTReg(0));
     return;
   }
+  TargetLowering *Target = Func->getTarget();
   Type Ty = Dest->getType();
   if (!Dest->hasReg()) {
     typename InstX86Base<Machine>::Traits::Address StackAddr(
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-            Func->getTarget())
+            Target)
             ->stackVarToAsmOperand(Dest));
     Asm->fstp(Ty, StackAddr);
   } else {
     // Dest is a physical (xmm) register, so st(0) needs to go through memory.
     // Hack this by creating a temporary stack slot, spilling st(0) there,
     // loading it into the xmm register, and deallocating the stack slot.
     Immediate Width(typeWidthInBytes(Ty));
     Asm->sub(IceType_i32,
              InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp, Width);
     typename InstX86Base<Machine>::Traits::Address StackSlot =
@@ skipping 42 matching lines @@
   this->emitTwoAddress(buf, this, Func);
 }
 
 template <class Machine>
 void InstX86Pextr<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 2);
   // pextrb and pextrd are SSE4.1 instructions.
+  TargetLowering *Target = Func->getTarget();
   assert(this->getSrc(0)->getType() == IceType_v8i16 ||
          this->getSrc(0)->getType() == IceType_v8i1 ||
          static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-             Func->getTarget())
+             Target)
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   Str << "\t" << this->Opcode
       << InstX86Base<Machine>::Traits::TypeAttributes[this->getSrc(0)
                                                           ->getType()]
              .PackString << "\t";
   this->getSrc(1)->emit(Func);
   Str << ", ";
   this->getSrc(0)->emit(Func);
   Str << ", ";
   Variable *Dest = this->getDest();
   // pextrw must take a register dest. There is an SSE4.1 version that takes a
   // memory dest, but we aren't using it. For uniformity, just restrict them
   // all to have a register dest for now.
   assert(Dest->hasReg());
   Dest->asType(IceType_i32, Dest->getRegNum())->emit(Func);
 }
 
 template <class Machine>
 void InstX86Pextr<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 2);
   // pextrb and pextrd are SSE4.1 instructions.
   const Variable *Dest = this->getDest();
   Type DispatchTy = InstX86Base<Machine>::Traits::getInVectorElementType(
       this->getSrc(0)->getType());
+  TargetLowering *Target = Func->getTarget();
   assert(DispatchTy == IceType_i16 ||
          static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-             Func->getTarget())
+             Target)
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   // pextrw must take a register dest. There is an SSE4.1 version that takes a
   // memory dest, but we aren't using it. For uniformity, just restrict them
   // all to have a register dest for now.
   assert(Dest->hasReg());
   // pextrw's Src(0) must be a register (both SSE4.1 and SSE2).
   assert(llvm::cast<Variable>(this->getSrc(0))->hasReg());
   static const typename InstX86Base<Machine>::Traits::Assembler::
       template ThreeOpImmEmitter<
           typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister>
           Emitter = {&InstX86Base<Machine>::Traits::Assembler::pextr, nullptr};
   emitIASThreeOpImmOps<
       Machine, typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
       typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
       InstX86Base<Machine>::Traits::getEncodedGPR,
       InstX86Base<Machine>::Traits::getEncodedXmm>(
       Func, DispatchTy, Dest, this->getSrc(0), this->getSrc(1), Emitter);
 }
 
 template <class Machine>
 void InstX86Pinsr<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 3);
   // pinsrb and pinsrd are SSE4.1 instructions.
+  TargetLowering *Target = Func->getTarget();
   assert(this->getDest()->getType() == IceType_v8i16 ||
          this->getDest()->getType() == IceType_v8i1 ||
          static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-             Func->getTarget())
+             Target)
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   Str << "\t" << this->Opcode
       << InstX86Base<
              Machine>::Traits::TypeAttributes[this->getDest()->getType()]
              .PackString << "\t";
   this->getSrc(2)->emit(Func);
   Str << ", ";
   Operand *Src1 = this->getSrc(1);
   if (const auto *Src1Var = llvm::dyn_cast<Variable>(Src1)) {
     // If src1 is a register, it should always be r32.
@@ skipping 12 matching lines @@
   this->getDest()->emit(Func);
 }
 
 template <class Machine>
 void InstX86Pinsr<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 3);
   assert(this->getDest() == this->getSrc(0));
   // pinsrb and pinsrd are SSE4.1 instructions.
   const Operand *Src0 = this->getSrc(1);
   Type DispatchTy = Src0->getType();
+  TargetLowering *Target = Func->getTarget();
   assert(DispatchTy == IceType_i16 ||
          static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-             Func->getTarget())
+             Target)
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   // If src1 is a register, it should always be r32 (this should fall out from
   // the encodings for ByteRegs overlapping the encodings for r32), but we have
   // to make sure the register allocator didn't choose an 8-bit high register
   // like "ah".
   if (BuildDefs::asserts()) {
     if (auto *Src0Var = llvm::dyn_cast<Variable>(Src0)) {
       if (Src0Var->hasReg()) {
         int32_t RegNum = Src0Var->getRegNum();
         int32_t BaseRegNum = InstX86Base<Machine>::Traits::getBaseReg(RegNum);
@@ skipping 67 matching lines @@
 
 template <class Machine>
 void InstX86Pop<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 0);
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   if (this->getDest()->hasReg()) {
     Asm->popl(InstX86Base<Machine>::Traits::getEncodedGPR(
         this->getDest()->getRegNum()));
   } else {
+    TargetLowering *Target = Func->getTarget();
     Asm->popl(
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-            Func->getTarget())
+            Target)
             ->stackVarToAsmOperand(this->getDest()));
   }
 }
 
 template <class Machine> void InstX86Pop<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   this->dumpDest(Func);
   Str << " = pop." << this->getDest()->getType() << " ";
 }
 
 template <class Machine>
 void InstX86AdjustStack<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\tsubl\t$" << Amount << ", %esp";
-  Func->getTarget()->updateStackAdjustment(Amount);
+  TargetLowering *Target = Func->getTarget();
+  Target->updateStackAdjustment(Amount);
 }
 
 template <class Machine>
 void InstX86AdjustStack<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   Asm->sub(IceType_i32,
            InstX86Base<Machine>::Traits::RegisterSet::Encoded_Reg_esp,
            Immediate(Amount));
-  Func->getTarget()->updateStackAdjustment(Amount);
+  TargetLowering *Target = Func->getTarget();
+  Target->updateStackAdjustment(Amount);
 }
 
 template <class Machine>
 void InstX86AdjustStack<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "esp = sub.i32 esp, " << Amount;
 }
 
@@ skipping 109 matching lines @@
   this->Dest->emit(Func);
 }
 
 template <class Machine>
 void InstX86Setcc<Machine>::emitIAS(const Cfg *Func) const {
   assert(Condition != InstX86Base<Machine>::Traits::Cond::Br_None);
   assert(this->getDest()->getType() == IceType_i1);
   assert(this->getSrcSize() == 0);
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
+  TargetLowering *Target = Func->getTarget();
   if (this->getDest()->hasReg())
     Asm->setcc(Condition, InstX86Base<Machine>::Traits::getEncodedByteReg(
                               this->getDest()->getRegNum()));
   else
     Asm->setcc(
         Condition,
         static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
-            Func->getTarget())
+            Target)
             ->stackVarToAsmOperand(this->getDest()));
   return;
 }
 
 template <class Machine>
 void InstX86Setcc<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "setcc."
@@ skipping 20 matching lines @@
 void InstX86Xadd<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 2);
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   Type Ty = this->getSrc(0)->getType();
   const auto Mem =
       llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
           this->getSrc(0));
   assert(Mem->getSegmentRegister() ==
          InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
+  TargetLowering *Target = Func->getTarget();
   const typename InstX86Base<Machine>::Traits::Address Addr =
-      Mem->toAsmAddress(Asm);
+      Mem->toAsmAddress(Asm, Target);
   const auto *VarReg = llvm::cast<Variable>(this->getSrc(1));
   assert(VarReg->hasReg());
   const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg =
       InstX86Base<Machine>::Traits::getEncodedGPR(VarReg->getRegNum());
   Asm->xadd(Ty, Addr, Reg, this->Locked);
 }
 
 template <class Machine>
 void InstX86Xadd<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
@@ skipping 35 matching lines @@
         InstX86Base<Machine>::Traits::getEncodedGPR(VarReg0->getRegNum());
     Asm->xchg(Ty, Reg0, Reg1);
     return;
   }
 
   const auto *Mem =
       llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
           this->getSrc(0));
   assert(Mem->getSegmentRegister() ==
          InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
+  TargetLowering *Target = Func->getTarget();
   const typename InstX86Base<Machine>::Traits::Address Addr =
-      Mem->toAsmAddress(Asm);
+      Mem->toAsmAddress(Asm, Target);
   Asm->xchg(Ty, Addr, Reg1);
 }
 
 template <class Machine>
 void InstX86Xchg<Machine>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Type Ty = this->getSrc(0)->getType();
   Str << "xchg." << Ty << " ";
@@ skipping 50 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "IACA_END";
 }
 
 } // end of namespace X86Internal
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX86BASEIMPL_H