MIPS: Remove soft-float support.

test/cctest/test-assembler-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 259 matching lines @@
     double h;
     double i;
   } T;
   T t;
 
   // Create a function that accepts &t, and loads, manipulates, and stores
   // the doubles t.a ... t.f.
   MacroAssembler assm(isolate, NULL, 0);
   Label L, C;
 
-  if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatureScope scope(&assm, FPU);
+  __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
+  __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
+  __ add_d(f8, f4, f6);
+  __ sdc1(f8, MemOperand(a0, OFFSET_OF(T, c)) );  // c = a + b.
 
-    __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
-    __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
-    __ add_d(f8, f4, f6);
-    __ sdc1(f8, MemOperand(a0, OFFSET_OF(T, c)) );  // c = a + b.
+  __ mov_d(f10, f8);  // c
+  __ neg_d(f12, f6);  // -b
+  __ sub_d(f10, f10, f12);
+  __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, d)) );  // d = c - (-b).
 
-    __ mov_d(f10, f8);  // c
-    __ neg_d(f12, f6);  // -b
-    __ sub_d(f10, f10, f12);
-    __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, d)) );  // d = c - (-b).
+  __ sdc1(f4, MemOperand(a0, OFFSET_OF(T, b)) );   // b = a.
 
-    __ sdc1(f4, MemOperand(a0, OFFSET_OF(T, b)) );   // b = a.
+  __ li(t0, 120);
+  __ mtc1(t0, f14);
+  __ cvt_d_w(f14, f14);   // f14 = 120.0.
+  __ mul_d(f10, f10, f14);
+  __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, e)) );  // e = d * 120 = 1.8066e16.
 
-    __ li(t0, 120);
-    __ mtc1(t0, f14);
-    __ cvt_d_w(f14, f14);   // f14 = 120.0.
-    __ mul_d(f10, f10, f14);
-    __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, e)) );  // e = d * 120 = 1.8066e16.
+  __ div_d(f12, f10, f4);
+  __ sdc1(f12, MemOperand(a0, OFFSET_OF(T, f)) );  // f = e / a = 120.44.
 
-    __ div_d(f12, f10, f4);
-    __ sdc1(f12, MemOperand(a0, OFFSET_OF(T, f)) );  // f = e / a = 120.44.
-
-    __ sqrt_d(f14, f12);
-    __ sdc1(f14, MemOperand(a0, OFFSET_OF(T, g)) );
-    // g = sqrt(f) = 10.97451593465515908537
+  __ sqrt_d(f14, f12);
+  __ sdc1(f14, MemOperand(a0, OFFSET_OF(T, g)) );
+  // g = sqrt(f) = 10.97451593465515908537
 
   if (kArchVariant == kMips32r2) {
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, h)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, i)) );
     __ madd_d(f14, f6, f4, f6);
     __ sdc1(f14, MemOperand(a0, OFFSET_OF(T, h)) );
   }
 
-    __ jr(ra);
-    __ nop();
+  __ jr(ra);
+  __ nop();
 
-    CodeDesc desc;
-    assm.GetCode(&desc);
-    Object* code = HEAP->CreateCode(
-        desc,
-        Code::ComputeFlags(Code::STUB),
-        Handle<Code>())->ToObjectChecked();
-    CHECK(code->IsCode());
-    F3 f = FUNCTION_CAST<F3>(Code::cast(code)->entry());
-    t.a = 1.5e14;
-    t.b = 2.75e11;
-    t.c = 0.0;
-    t.d = 0.0;
-    t.e = 0.0;
-    t.f = 0.0;
-    t.h = 1.5;
-    t.i = 2.75;
-    Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
-    USE(dummy);
-    CHECK_EQ(1.5e14, t.a);
-    CHECK_EQ(1.5e14, t.b);
-    CHECK_EQ(1.50275e14, t.c);
-    CHECK_EQ(1.50550e14, t.d);
-    CHECK_EQ(1.8066e16, t.e);
-    CHECK_EQ(120.44, t.f);
-    CHECK_EQ(10.97451593465515908537, t.g);
-    CHECK_EQ(6.875, t.h);
-  }
+  CodeDesc desc;
+  assm.GetCode(&desc);
+  Object* code = HEAP->CreateCode(
+      desc,
+      Code::ComputeFlags(Code::STUB),
+      Handle<Code>())->ToObjectChecked();
+  CHECK(code->IsCode());
+  F3 f = FUNCTION_CAST<F3>(Code::cast(code)->entry());
+  t.a = 1.5e14;
+  t.b = 2.75e11;
+  t.c = 0.0;
+  t.d = 0.0;
+  t.e = 0.0;
+  t.f = 0.0;
+  t.h = 1.5;
+  t.i = 2.75;
+  Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
+  USE(dummy);
+  CHECK_EQ(1.5e14, t.a);
+  CHECK_EQ(1.5e14, t.b);
+  CHECK_EQ(1.50275e14, t.c);
+  CHECK_EQ(1.50550e14, t.d);
+  CHECK_EQ(1.8066e16, t.e);
+  CHECK_EQ(120.44, t.f);
+  CHECK_EQ(10.97451593465515908537, t.g);
+  CHECK_EQ(6.875, t.h);
 }
 
 
 TEST(MIPS4) {
   // Test moves between floating point and integer registers.
   CcTest::InitializeVM();
   Isolate* isolate = Isolate::Current();
   HandleScope scope(isolate);
 
   typedef struct {
     double a;
     double b;
     double c;
   } T;
   T t;
 
   Assembler assm(isolate, NULL, 0);
   Label L, C;
 
-  if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatureScope scope(&assm, FPU);
+  __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
+  __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
 
-    __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
-    __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
+  // Swap f4 and f6, by using four integer registers, t0-t3.
+  __ mfc1(t0, f4);
+  __ mfc1(t1, f5);
+  __ mfc1(t2, f6);
+  __ mfc1(t3, f7);
 
-    // Swap f4 and f6, by using four integer registers, t0-t3.
-    __ mfc1(t0, f4);
-    __ mfc1(t1, f5);
-    __ mfc1(t2, f6);
-    __ mfc1(t3, f7);
+  __ mtc1(t0, f6);
+  __ mtc1(t1, f7);
+  __ mtc1(t2, f4);
+  __ mtc1(t3, f5);
 
-    __ mtc1(t0, f6);
-    __ mtc1(t1, f7);
-    __ mtc1(t2, f4);
-    __ mtc1(t3, f5);
+  // Store the swapped f4 and f5 back to memory.
+  __ sdc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
+  __ sdc1(f6, MemOperand(a0, OFFSET_OF(T, c)) );
 
-    // Store the swapped f4 and f5 back to memory.
-    __ sdc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
-    __ sdc1(f6, MemOperand(a0, OFFSET_OF(T, c)) );
+  __ jr(ra);
+  __ nop();
 
-    __ jr(ra);
-    __ nop();
+  CodeDesc desc;
+  assm.GetCode(&desc);
+  Object* code = HEAP->CreateCode(
+      desc,
+      Code::ComputeFlags(Code::STUB),
+      Handle<Code>())->ToObjectChecked();
+  CHECK(code->IsCode());
+  F3 f = FUNCTION_CAST<F3>(Code::cast(code)->entry());
+  t.a = 1.5e22;
+  t.b = 2.75e11;
+  t.c = 17.17;
+  Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
+  USE(dummy);
 
-    CodeDesc desc;
-    assm.GetCode(&desc);
-    Object* code = HEAP->CreateCode(
-        desc,
-        Code::ComputeFlags(Code::STUB),
-        Handle<Code>())->ToObjectChecked();
-    CHECK(code->IsCode());
-    F3 f = FUNCTION_CAST<F3>(Code::cast(code)->entry());
-    t.a = 1.5e22;
-    t.b = 2.75e11;
-    t.c = 17.17;
-    Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
-    USE(dummy);
-
-    CHECK_EQ(2.75e11, t.a);
-    CHECK_EQ(2.75e11, t.b);
-    CHECK_EQ(1.5e22, t.c);
-  }
+  CHECK_EQ(2.75e11, t.a);
+  CHECK_EQ(2.75e11, t.b);
+  CHECK_EQ(1.5e22, t.c);
 }
 
 
 TEST(MIPS5) {
   // Test conversions between doubles and integers.
   CcTest::InitializeVM();
   Isolate* isolate = Isolate::Current();
   HandleScope scope(isolate);
 
   typedef struct {
     double a;
     double b;
     int i;
     int j;
   } T;
   T t;
 
   Assembler assm(isolate, NULL, 0);
   Label L, C;
 
-  if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatureScope scope(&assm, FPU);
+  // Load all structure elements to registers.
+  __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
+  __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
+  __ lw(t0, MemOperand(a0, OFFSET_OF(T, i)) );
+  __ lw(t1, MemOperand(a0, OFFSET_OF(T, j)) );
 
-    // Load all structure elements to registers.
-    __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
-    __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
-    __ lw(t0, MemOperand(a0, OFFSET_OF(T, i)) );
-    __ lw(t1, MemOperand(a0, OFFSET_OF(T, j)) );
+  // Convert double in f4 to int in element i.
+  __ cvt_w_d(f8, f4);
+  __ mfc1(t2, f8);
+  __ sw(t2, MemOperand(a0, OFFSET_OF(T, i)) );
 
-    // Convert double in f4 to int in element i.
-    __ cvt_w_d(f8, f4);
-    __ mfc1(t2, f8);
-    __ sw(t2, MemOperand(a0, OFFSET_OF(T, i)) );
+  // Convert double in f6 to int in element j.
+  __ cvt_w_d(f10, f6);
+  __ mfc1(t3, f10);
+  __ sw(t3, MemOperand(a0, OFFSET_OF(T, j)) );
 
-    // Convert double in f6 to int in element j.
-    __ cvt_w_d(f10, f6);
-    __ mfc1(t3, f10);
-    __ sw(t3, MemOperand(a0, OFFSET_OF(T, j)) );
+  // Convert int in original i (t0) to double in a.
+  __ mtc1(t0, f12);
+  __ cvt_d_w(f0, f12);
+  __ sdc1(f0, MemOperand(a0, OFFSET_OF(T, a)) );
 
-    // Convert int in original i (t0) to double in a.
-    __ mtc1(t0, f12);
-    __ cvt_d_w(f0, f12);
-    __ sdc1(f0, MemOperand(a0, OFFSET_OF(T, a)) );
+  // Convert int in original j (t1) to double in b.
+  __ mtc1(t1, f14);
+  __ cvt_d_w(f2, f14);
+  __ sdc1(f2, MemOperand(a0, OFFSET_OF(T, b)) );
 
-    // Convert int in original j (t1) to double in b.
-    __ mtc1(t1, f14);
-    __ cvt_d_w(f2, f14);
-    __ sdc1(f2, MemOperand(a0, OFFSET_OF(T, b)) );
+  __ jr(ra);
+  __ nop();
 
-    __ jr(ra);
-    __ nop();
+  CodeDesc desc;
+  assm.GetCode(&desc);
+  Object* code = HEAP->CreateCode(
+      desc,
+      Code::ComputeFlags(Code::STUB),
+      Handle<Code>())->ToObjectChecked();
+  CHECK(code->IsCode());
+  F3 f = FUNCTION_CAST<F3>(Code::cast(code)->entry());
+  t.a = 1.5e4;
+  t.b = 2.75e8;
+  t.i = 12345678;
+  t.j = -100000;
+  Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
+  USE(dummy);
 
-    CodeDesc desc;
-    assm.GetCode(&desc);
-    Object* code = HEAP->CreateCode(
-        desc,
-        Code::ComputeFlags(Code::STUB),
-        Handle<Code>())->ToObjectChecked();
-    CHECK(code->IsCode());
-    F3 f = FUNCTION_CAST<F3>(Code::cast(code)->entry());
-    t.a = 1.5e4;
-    t.b = 2.75e8;
-    t.i = 12345678;
-    t.j = -100000;
-    Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
-    USE(dummy);
-
-    CHECK_EQ(12345678.0, t.a);
-    CHECK_EQ(-100000.0, t.b);
-    CHECK_EQ(15000, t.i);
-    CHECK_EQ(275000000, t.j);
-  }
+  CHECK_EQ(12345678.0, t.a);
+  CHECK_EQ(-100000.0, t.b);
+  CHECK_EQ(15000, t.i);
+  CHECK_EQ(275000000, t.j);
 }
 
 
 TEST(MIPS6) {
   // Test simple memory loads and stores.
   CcTest::InitializeVM();
   Isolate* isolate = Isolate::Current();
   HandleScope scope(isolate);
 
   typedef struct {
@@ skipping 78 matching lines @@
     double f;
     int32_t result;
   } T;
   T t;
 
   // Create a function that accepts &t, and loads, manipulates, and stores
   // the doubles t.a ... t.f.
   MacroAssembler assm(isolate, NULL, 0);
   Label neither_is_nan, less_than, outa_here;
 
-  if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatureScope scope(&assm, FPU);
+  __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
+  __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
+  __ c(UN, D, f4, f6);
+  __ bc1f(&neither_is_nan);
+  __ nop();
+  __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) );
+  __ Branch(&outa_here);
 
-    __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
-    __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
-    __ c(UN, D, f4, f6);
-    __ bc1f(&neither_is_nan);
-    __ nop();
-    __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) );
-    __ Branch(&outa_here);
+  __ bind(&neither_is_nan);
 
-    __ bind(&neither_is_nan);
+  if (kArchVariant == kLoongson) {
+    __ c(OLT, D, f6, f4);
+    __ bc1t(&less_than);
+  } else {
+    __ c(OLT, D, f6, f4, 2);
+    __ bc1t(&less_than, 2);
+  }
+  __ nop();
+  __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) );
+  __ Branch(&outa_here);
 
-    if (kArchVariant == kLoongson) {
-      __ c(OLT, D, f6, f4);
-      __ bc1t(&less_than);
-    } else {
-      __ c(OLT, D, f6, f4, 2);
-      __ bc1t(&less_than, 2);
-    }
-    __ nop();
-    __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) );
-    __ Branch(&outa_here);
-
-    __ bind(&less_than);
-    __ Addu(t0, zero_reg, Operand(1));
-    __ sw(t0, MemOperand(a0, OFFSET_OF(T, result)) );  // Set true.
+  __ bind(&less_than);
+  __ Addu(t0, zero_reg, Operand(1));
+  __ sw(t0, MemOperand(a0, OFFSET_OF(T, result)) );  // Set true.
 
 
-    // This test-case should have additional tests.
+  // This test-case should have additional tests.
 
-    __ bind(&outa_here);
+  __ bind(&outa_here);
 
-    __ jr(ra);
-    __ nop();
+  __ jr(ra);
+  __ nop();
 
-    CodeDesc desc;
-    assm.GetCode(&desc);
-    Object* code = HEAP->CreateCode(
-        desc,
-        Code::ComputeFlags(Code::STUB),
-        Handle<Code>())->ToObjectChecked();
-    CHECK(code->IsCode());
-    F3 f = FUNCTION_CAST<F3>(Code::cast(code)->entry());
-    t.a = 1.5e14;
-    t.b = 2.75e11;
-    t.c = 2.0;
-    t.d = -4.0;
-    t.e = 0.0;
-    t.f = 0.0;
-    t.result = 0;
-    Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
-    USE(dummy);
-    CHECK_EQ(1.5e14, t.a);
-    CHECK_EQ(2.75e11, t.b);
-    CHECK_EQ(1, t.result);
-  }
+  CodeDesc desc;
+  assm.GetCode(&desc);
+  Object* code = HEAP->CreateCode(
+      desc,
+      Code::ComputeFlags(Code::STUB),
+      Handle<Code>())->ToObjectChecked();
+  CHECK(code->IsCode());
+  F3 f = FUNCTION_CAST<F3>(Code::cast(code)->entry());
+  t.a = 1.5e14;
+  t.b = 2.75e11;
+  t.c = 2.0;
+  t.d = -4.0;
+  t.e = 0.0;
+  t.f = 0.0;
+  t.result = 0;
+  Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
+  USE(dummy);
+  CHECK_EQ(1.5e14, t.a);
+  CHECK_EQ(2.75e11, t.b);
+  CHECK_EQ(1, t.result);
 }
 
 
 TEST(MIPS8) {
   // Test ROTR and ROTRV instructions.
   CcTest::InitializeVM();
   Isolate* isolate = Isolate::Current();
   HandleScope scope(isolate);
 
   typedef struct {
@@ skipping 139 matching lines @@
     int32_t long_hi;
     int32_t long_lo;
     int32_t b_long_hi;
     int32_t b_long_lo;
   } T;
   T t;
 
   Assembler assm(isolate, NULL, 0);
   Label L, C;
 
-  if (CpuFeatures::IsSupported(FPU) && kArchVariant == kMips32r2) {
-    CpuFeatureScope scope(&assm, FPU);
-
+  if (kArchVariant == kMips32r2) {
     // Load all structure elements to registers.
     __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, a)));
 
     // Save the raw bits of the double.
     __ mfc1(t0, f0);
     __ mfc1(t1, f1);
     __ sw(t0, MemOperand(a0, OFFSET_OF(T, dbl_mant)));
     __ sw(t1, MemOperand(a0, OFFSET_OF(T, dbl_exp)));
 
     // Convert double in f0 to long, save hi/lo parts.
@@ skipping 285 matching lines @@
     double cvt_small_out;
     uint32_t trunc_big_out;
     uint32_t trunc_small_out;
     uint32_t cvt_big_in;
     uint32_t cvt_small_in;
   } T;
   T t;
 
   MacroAssembler assm(isolate, NULL, 0);
 
-  if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatureScope scope(&assm, FPU);
+  __ sw(t0, MemOperand(a0, OFFSET_OF(T, cvt_small_in)));
+  __ Cvt_d_uw(f10, t0, f22);
+  __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, cvt_small_out)));
 
-    __ sw(t0, MemOperand(a0, OFFSET_OF(T, cvt_small_in)));
-    __ Cvt_d_uw(f10, t0, f22);
-    __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, cvt_small_out)));
+  __ Trunc_uw_d(f10, f10, f22);
+  __ swc1(f10, MemOperand(a0, OFFSET_OF(T, trunc_small_out)));
 
-    __ Trunc_uw_d(f10, f10, f22);
-    __ swc1(f10, MemOperand(a0, OFFSET_OF(T, trunc_small_out)));
+  __ sw(t0, MemOperand(a0, OFFSET_OF(T, cvt_big_in)));
+  __ Cvt_d_uw(f8, t0, f22);
+  __ sdc1(f8, MemOperand(a0, OFFSET_OF(T, cvt_big_out)));
 
-    __ sw(t0, MemOperand(a0, OFFSET_OF(T, cvt_big_in)));
-    __ Cvt_d_uw(f8, t0, f22);
-    __ sdc1(f8, MemOperand(a0, OFFSET_OF(T, cvt_big_out)));
+  __ Trunc_uw_d(f8, f8, f22);
+  __ swc1(f8, MemOperand(a0, OFFSET_OF(T, trunc_big_out)));
 
-    __ Trunc_uw_d(f8, f8, f22);
-    __ swc1(f8, MemOperand(a0, OFFSET_OF(T, trunc_big_out)));
+  __ jr(ra);
+  __ nop();
 
-    __ jr(ra);
-    __ nop();
+  CodeDesc desc;
+  assm.GetCode(&desc);
+  Object* code = HEAP->CreateCode(
+      desc,
+      Code::ComputeFlags(Code::STUB),
+      Handle<Code>())->ToObjectChecked();
+  CHECK(code->IsCode());
+  F3 f = FUNCTION_CAST<F3>(Code::cast(code)->entry());
 
-    CodeDesc desc;
-    assm.GetCode(&desc);
-    Object* code = HEAP->CreateCode(
-        desc,
-        Code::ComputeFlags(Code::STUB),
-        Handle<Code>())->ToObjectChecked();
-    CHECK(code->IsCode());
-    F3 f = FUNCTION_CAST<F3>(Code::cast(code)->entry());
+  t.cvt_big_in = 0xFFFFFFFF;
+  t.cvt_small_in  = 333;
 
-    t.cvt_big_in = 0xFFFFFFFF;
-    t.cvt_small_in  = 333;
+  Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
+  USE(dummy);
 
-    Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
-    USE(dummy);
+  CHECK_EQ(t.cvt_big_out, static_cast<double>(t.cvt_big_in));
+  CHECK_EQ(t.cvt_small_out, static_cast<double>(t.cvt_small_in));
 
-    CHECK_EQ(t.cvt_big_out, static_cast<double>(t.cvt_big_in));
-    CHECK_EQ(t.cvt_small_out, static_cast<double>(t.cvt_small_in));
-
-    CHECK_EQ(static_cast<int>(t.trunc_big_out), static_cast<int>(t.cvt_big_in));
-    CHECK_EQ(static_cast<int>(t.trunc_small_out),
-             static_cast<int>(t.cvt_small_in));
-  }
+  CHECK_EQ(static_cast<int>(t.trunc_big_out), static_cast<int>(t.cvt_big_in));
+  CHECK_EQ(static_cast<int>(t.trunc_small_out),
+           static_cast<int>(t.cvt_small_in));
 }
 
 
 TEST(MIPS14) {
   // Test round, floor, ceil, trunc, cvt.
   CcTest::InitializeVM();
   Isolate* isolate = Isolate::Current();
   HandleScope scope(isolate);
 
 #define ROUND_STRUCT_ELEMENT(x) \
@@ skipping 22 matching lines @@
     ROUND_STRUCT_ELEMENT(ceil)
     ROUND_STRUCT_ELEMENT(trunc)
     ROUND_STRUCT_ELEMENT(cvt)
   } T;
   T t;
 
 #undef ROUND_STRUCT_ELEMENT
 
   MacroAssembler assm(isolate, NULL, 0);
 
-  if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatureScope scope(&assm, FPU);
+  // Save FCSR.
+  __ cfc1(a1, FCSR);
+  // Disable FPU exceptions.
+  __ ctc1(zero_reg, FCSR);
+#define RUN_ROUND_TEST(x) \
+  __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, round_up_in))); \
+  __ x##_w_d(f0, f0); \
+  __ swc1(f0, MemOperand(a0, OFFSET_OF(T, x##_up_out))); \
+  \
+  __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, round_down_in))); \
+  __ x##_w_d(f0, f0); \
+  __ swc1(f0, MemOperand(a0, OFFSET_OF(T, x##_down_out))); \
+  \
+  __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, neg_round_up_in))); \
+  __ x##_w_d(f0, f0); \
+  __ swc1(f0, MemOperand(a0, OFFSET_OF(T, neg_##x##_up_out))); \
+  \
+  __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, neg_round_down_in))); \
+  __ x##_w_d(f0, f0); \
+  __ swc1(f0, MemOperand(a0, OFFSET_OF(T, neg_##x##_down_out))); \
+  \
+  __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, err1_in))); \
+  __ ctc1(zero_reg, FCSR); \
+  __ x##_w_d(f0, f0); \
+  __ cfc1(a2, FCSR); \
+  __ sw(a2, MemOperand(a0, OFFSET_OF(T, x##_err1_out))); \
+  \
+  __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, err2_in))); \
+  __ ctc1(zero_reg, FCSR); \
+  __ x##_w_d(f0, f0); \
+  __ cfc1(a2, FCSR); \
+  __ sw(a2, MemOperand(a0, OFFSET_OF(T, x##_err2_out))); \
+  \
+  __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, err3_in))); \
+  __ ctc1(zero_reg, FCSR); \
+  __ x##_w_d(f0, f0); \
+  __ cfc1(a2, FCSR); \
+  __ sw(a2, MemOperand(a0, OFFSET_OF(T, x##_err3_out))); \
+  \
+  __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, err4_in))); \
+  __ ctc1(zero_reg, FCSR); \
+  __ x##_w_d(f0, f0); \
+  __ cfc1(a2, FCSR); \
+  __ sw(a2, MemOperand(a0, OFFSET_OF(T, x##_err4_out))); \
+  __ swc1(f0, MemOperand(a0, OFFSET_OF(T, x##_invalid_result)));
 
-    // Save FCSR.
-    __ cfc1(a1, FCSR);
-    // Disable FPU exceptions.
-    __ ctc1(zero_reg, FCSR);
-#define RUN_ROUND_TEST(x) \
-    __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, round_up_in))); \
-    __ x##_w_d(f0, f0); \
-    __ swc1(f0, MemOperand(a0, OFFSET_OF(T, x##_up_out))); \
-    \
-    __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, round_down_in))); \
-    __ x##_w_d(f0, f0); \
-    __ swc1(f0, MemOperand(a0, OFFSET_OF(T, x##_down_out))); \
-    \
-    __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, neg_round_up_in))); \
-    __ x##_w_d(f0, f0); \
-    __ swc1(f0, MemOperand(a0, OFFSET_OF(T, neg_##x##_up_out))); \
-    \
-    __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, neg_round_down_in))); \
-    __ x##_w_d(f0, f0); \
-    __ swc1(f0, MemOperand(a0, OFFSET_OF(T, neg_##x##_down_out))); \
-    \
-    __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, err1_in))); \
-    __ ctc1(zero_reg, FCSR); \
-    __ x##_w_d(f0, f0); \
-    __ cfc1(a2, FCSR); \
-    __ sw(a2, MemOperand(a0, OFFSET_OF(T, x##_err1_out))); \
-    \
-    __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, err2_in))); \
-    __ ctc1(zero_reg, FCSR); \
-    __ x##_w_d(f0, f0); \
-    __ cfc1(a2, FCSR); \
-    __ sw(a2, MemOperand(a0, OFFSET_OF(T, x##_err2_out))); \
-    \
-    __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, err3_in))); \
-    __ ctc1(zero_reg, FCSR); \
-    __ x##_w_d(f0, f0); \
-    __ cfc1(a2, FCSR); \
-    __ sw(a2, MemOperand(a0, OFFSET_OF(T, x##_err3_out))); \
-    \
-    __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, err4_in))); \
-    __ ctc1(zero_reg, FCSR); \
-    __ x##_w_d(f0, f0); \
-    __ cfc1(a2, FCSR); \
-    __ sw(a2, MemOperand(a0, OFFSET_OF(T, x##_err4_out))); \
-    __ swc1(f0, MemOperand(a0, OFFSET_OF(T, x##_invalid_result)));
+  RUN_ROUND_TEST(round)
+  RUN_ROUND_TEST(floor)
+  RUN_ROUND_TEST(ceil)
+  RUN_ROUND_TEST(trunc)
+  RUN_ROUND_TEST(cvt)
 
-    RUN_ROUND_TEST(round)
-    RUN_ROUND_TEST(floor)
-    RUN_ROUND_TEST(ceil)
-    RUN_ROUND_TEST(trunc)
-    RUN_ROUND_TEST(cvt)
+  // Restore FCSR.
+  __ ctc1(a1, FCSR);
 
-    // Restore FCSR.
-    __ ctc1(a1, FCSR);
+  __ jr(ra);
+  __ nop();
 
-    __ jr(ra);
-    __ nop();
+  CodeDesc desc;
+  assm.GetCode(&desc);
+  Object* code = HEAP->CreateCode(
+      desc,
+      Code::ComputeFlags(Code::STUB),
+      Handle<Code>())->ToObjectChecked();
+  CHECK(code->IsCode());
+  F3 f = FUNCTION_CAST<F3>(Code::cast(code)->entry());
 
-    CodeDesc desc;
-    assm.GetCode(&desc);
-    Object* code = HEAP->CreateCode(
-        desc,
-        Code::ComputeFlags(Code::STUB),
-        Handle<Code>())->ToObjectChecked();
-    CHECK(code->IsCode());
-    F3 f = FUNCTION_CAST<F3>(Code::cast(code)->entry());
+  t.round_up_in = 123.51;
+  t.round_down_in = 123.49;
+  t.neg_round_up_in = -123.5;
+  t.neg_round_down_in = -123.49;
+  t.err1_in = 123.51;
+  t.err2_in = 1;
+  t.err3_in = static_cast<double>(1) + 0xFFFFFFFF;
+  t.err4_in = NAN;
 
-    t.round_up_in = 123.51;
-    t.round_down_in = 123.49;
-    t.neg_round_up_in = -123.5;
-    t.neg_round_down_in = -123.49;
-    t.err1_in = 123.51;
-    t.err2_in = 1;
-    t.err3_in = static_cast<double>(1) + 0xFFFFFFFF;
-    t.err4_in = NAN;
-
-    Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
-    USE(dummy);
+  Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
+  USE(dummy);
 
 #define GET_FPU_ERR(x) (static_cast<int>(x & kFCSRFlagMask))
 #define CHECK_ROUND_RESULT(type) \
   CHECK(GET_FPU_ERR(t.type##_err1_out) & kFCSRInexactFlagMask); \
   CHECK_EQ(0, GET_FPU_ERR(t.type##_err2_out)); \
   CHECK(GET_FPU_ERR(t.type##_err3_out) & kFCSRInvalidOpFlagMask); \
   CHECK(GET_FPU_ERR(t.type##_err4_out) & kFCSRInvalidOpFlagMask); \
   CHECK_EQ(kFPUInvalidResult, t.type##_invalid_result);
 
-    CHECK_ROUND_RESULT(round);
-    CHECK_ROUND_RESULT(floor);
-    CHECK_ROUND_RESULT(ceil);
-    CHECK_ROUND_RESULT(cvt);
-  }
+  CHECK_ROUND_RESULT(round);
+  CHECK_ROUND_RESULT(floor);
+  CHECK_ROUND_RESULT(ceil);
+  CHECK_ROUND_RESULT(cvt);
 }
 
 
 TEST(MIPS15) {
   // Test chaining of label usages within instructions (issue 1644).
   CcTest::InitializeVM();
   Isolate* isolate = Isolate::Current();
   HandleScope scope(isolate);
   Assembler assm(isolate, NULL, 0);
 
   Label target;
   __ beq(v0, v1, &target);
   __ nop();
   __ bne(v0, v1, &target);
   __ nop();
   __ bind(&target);
   __ nop();
 }
 
 #undef __