MIPS: Remove soft-float support.

src/mips/code-stubs-mips.h

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 44 matching lines @@
 
   Major MajorKey() { return TranscendentalCache; }
   int MinorKey() { return type_ | argument_type_; }
   Runtime::FunctionId RuntimeFunction();
 };
 
 
 class StoreBufferOverflowStub: public PlatformCodeStub {
  public:
   explicit StoreBufferOverflowStub(SaveFPRegsMode save_fp)
-      : save_doubles_(save_fp) {
-    ASSERT(CpuFeatures::IsSafeForSnapshot(FPU) || save_fp == kDontSaveFPRegs);
-  }
+      : save_doubles_(save_fp) {}
 
   void Generate(MacroAssembler* masm);
 
   virtual bool IsPregenerated() { return true; }
   static void GenerateFixedRegStubsAheadOfTime(Isolate* isolate);
   virtual bool SometimesSetsUpAFrame() { return false; }
 
  private:
   SaveFPRegsMode save_doubles_;
 
@@ skipping 401 matching lines @@
     void Restore(MacroAssembler* masm) {
       masm->pop(scratch1_);
     }
 
     // If we have to call into C then we need to save and restore all caller-
     // saved registers that were not already preserved.  The scratch registers
     // will be restored by other means so we don't bother pushing them here.
     void SaveCallerSaveRegisters(MacroAssembler* masm, SaveFPRegsMode mode) {
       masm->MultiPush((kJSCallerSaved | ra.bit()) & ~scratch1_.bit());
       if (mode == kSaveFPRegs) {
-        CpuFeatureScope scope(masm, FPU);
         masm->MultiPushFPU(kCallerSavedFPU);
       }
     }
 
     inline void RestoreCallerSaveRegisters(MacroAssembler*masm,
                                            SaveFPRegsMode mode) {
       if (mode == kSaveFPRegs) {
-        CpuFeatureScope scope(masm, FPU);
         masm->MultiPopFPU(kCallerSavedFPU);
       }
       masm->MultiPop((kJSCallerSaved | ra.bit()) & ~scratch1_.bit());
     }
 
     inline Register object() { return object_; }
     inline Register address() { return address_; }
     inline Register scratch0() { return scratch0_; }
     inline Register scratch1() { return scratch1_; }
 
@@ skipping 170 matching lines @@
                                 Register object,
                                 Register dst,
                                 Register heap_number_map,
                                 Register scratch1,
                                 Register scratch2,
                                 Register scratch3,
                                 FPURegister double_scratch0,
                                 FPURegister double_scratch1,
                                 Label* not_int32);
 
-  // Generate non FPU code to check if a double can be exactly represented by a
-  // 32-bit integer. This does not check for 0 or -0, which need
-  // to be checked for separately.
-  // Control jumps to not_int32 if the value is not a 32-bit integer, and falls
-  // through otherwise.
-  // src1 and src2 will be cloberred.
-  //
-  // Expected input:
-  // - src1: higher (exponent) part of the double value.
-  // - src2: lower (mantissa) part of the double value.
-  // Output status:
-  // - dst: 32 higher bits of the mantissa. (mantissa[51:20])
-  // - src2: contains 1.
-  // - other registers are clobbered.
-  static void DoubleIs32BitInteger(MacroAssembler* masm,
-                                   Register src1,
-                                   Register src2,
-                                   Register dst,
-                                   Register scratch,
-                                   Label* not_int32);
-
   // Generates code to call a C function to do a double operation using core
   // registers. (Used when FPU is not supported.)
   // This code never falls through, but returns with a heap number containing
   // the result in v0.
   // Register heapnumber_result must be a heap number in which the
   // result of the operation will be stored.
   // Requires the following layout on entry:
   // a0: Left value (least significant part of mantissa).
   // a1: Left value (sign, exponent, top of mantissa).
   // a2: Right value (least significant part of mantissa).
@@ skipping 68 matching lines @@
 
   class LookupModeBits: public BitField<LookupMode, 0, 1> {};
 
   LookupMode mode_;
 };
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_MIPS_CODE_STUBS_ARM_H_