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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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73 #if(defined(__mips_hard_float) && __mips_hard_float != 0) | 73 #if(defined(__mips_hard_float) && __mips_hard_float != 0) |
74 answer |= static_cast<uint64_t>(1) << FPU; | 74 answer |= static_cast<uint64_t>(1) << FPU; |
75 #endif // defined(__mips_hard_float) && __mips_hard_float != 0 | 75 #endif // defined(__mips_hard_float) && __mips_hard_float != 0 |
76 #endif // def __mips__ | 76 #endif // def __mips__ |
77 | 77 |
78 return answer; | 78 return answer; |
79 } | 79 } |
80 | 80 |
81 | 81 |
82 const char* DoubleRegister::AllocationIndexToString(int index) { | 82 const char* DoubleRegister::AllocationIndexToString(int index) { |
83 if (CpuFeatures::IsSupported(FPU)) { | 83 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); |
84 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); | 84 const char* const names[] = { |
85 const char* const names[] = { | 85 "f0", |
86 "f0", | 86 "f2", |
87 "f2", | 87 "f4", |
88 "f4", | 88 "f6", |
89 "f6", | 89 "f8", |
90 "f8", | 90 "f10", |
91 "f10", | 91 "f12", |
92 "f12", | 92 "f14", |
93 "f14", | 93 "f16", |
94 "f16", | 94 "f18", |
95 "f18", | 95 "f20", |
96 "f20", | 96 "f22", |
97 "f22", | 97 "f24", |
98 "f24", | 98 "f26" |
99 "f26" | 99 }; |
100 }; | 100 return names[index]; |
101 return names[index]; | |
102 } else { | |
103 ASSERT(index == 0); | |
104 return "sfpd0"; | |
105 } | |
106 } | 101 } |
107 | 102 |
108 | 103 |
109 void CpuFeatures::Probe() { | 104 void CpuFeatures::Probe() { |
110 unsigned standard_features = (OS::CpuFeaturesImpliedByPlatform() | | 105 unsigned standard_features = (OS::CpuFeaturesImpliedByPlatform() | |
111 CpuFeaturesImpliedByCompiler()); | 106 CpuFeaturesImpliedByCompiler()); |
112 ASSERT(supported_ == 0 || supported_ == standard_features); | 107 ASSERT(supported_ == 0 || supported_ == standard_features); |
113 #ifdef DEBUG | 108 #ifdef DEBUG |
114 initialized_ = true; | 109 initialized_ = true; |
115 #endif | 110 #endif |
116 | 111 |
117 // Get the features implied by the OS and the compiler settings. This is the | 112 // Get the features implied by the OS and the compiler settings. This is the |
118 // minimal set of features which is also allowed for generated code in the | 113 // minimal set of features which is also allowed for generated code in the |
119 // snapshot. | 114 // snapshot. |
120 supported_ |= standard_features; | 115 supported_ |= standard_features; |
121 | 116 |
122 if (Serializer::enabled()) { | 117 if (Serializer::enabled()) { |
123 // No probing for features if we might serialize (generate snapshot). | 118 // No probing for features if we might serialize (generate snapshot). |
124 return; | 119 return; |
125 } | 120 } |
126 | 121 |
127 // If the compiler is allowed to use fpu then we can use fpu too in our | 122 // If the compiler is allowed to use fpu then we can use fpu too in our |
128 // code generation. | 123 // code generation. |
129 #if !defined(__mips__) | 124 #if !defined(__mips__) |
130 // For the simulator=mips build, use FPU when FLAG_enable_fpu is enabled. | 125 // For the simulator build, use FPU. |
131 if (FLAG_enable_fpu) { | 126 supported_ |= static_cast<uint64_t>(1) << FPU; |
132 supported_ |= static_cast<uint64_t>(1) << FPU; | |
133 } | |
134 #else | 127 #else |
135 // Probe for additional features not already known to be available. | 128 // Probe for additional features not already known to be available. |
136 if (OS::MipsCpuHasFeature(FPU)) { | 129 if (OS::MipsCpuHasFeature(FPU)) { |
137 // This implementation also sets the FPU flags if | 130 // This implementation also sets the FPU flags if |
138 // runtime detection of FPU returns true. | 131 // runtime detection of FPU returns true. |
139 supported_ |= static_cast<uint64_t>(1) << FPU; | 132 supported_ |= static_cast<uint64_t>(1) << FPU; |
140 found_by_runtime_probing_only_ |= static_cast<uint64_t>(1) << FPU; | 133 found_by_runtime_probing_only_ |= static_cast<uint64_t>(1) << FPU; |
141 } | 134 } |
142 #endif | 135 #endif |
143 } | 136 } |
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869 } | 862 } |
870 | 863 |
871 | 864 |
872 void Assembler::GenInstrRegister(Opcode opcode, | 865 void Assembler::GenInstrRegister(Opcode opcode, |
873 SecondaryField fmt, | 866 SecondaryField fmt, |
874 FPURegister ft, | 867 FPURegister ft, |
875 FPURegister fs, | 868 FPURegister fs, |
876 FPURegister fd, | 869 FPURegister fd, |
877 SecondaryField func) { | 870 SecondaryField func) { |
878 ASSERT(fd.is_valid() && fs.is_valid() && ft.is_valid()); | 871 ASSERT(fd.is_valid() && fs.is_valid() && ft.is_valid()); |
879 ASSERT(IsEnabled(FPU)); | |
880 Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift) | 872 Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift) |
881 | (fd.code() << kFdShift) | func; | 873 | (fd.code() << kFdShift) | func; |
882 emit(instr); | 874 emit(instr); |
883 } | 875 } |
884 | 876 |
885 | 877 |
886 void Assembler::GenInstrRegister(Opcode opcode, | 878 void Assembler::GenInstrRegister(Opcode opcode, |
887 FPURegister fr, | 879 FPURegister fr, |
888 FPURegister ft, | 880 FPURegister ft, |
889 FPURegister fs, | 881 FPURegister fs, |
890 FPURegister fd, | 882 FPURegister fd, |
891 SecondaryField func) { | 883 SecondaryField func) { |
892 ASSERT(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid()); | 884 ASSERT(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid()); |
893 ASSERT(IsEnabled(FPU)); | |
894 Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift) | 885 Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift) |
895 | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func; | 886 | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func; |
896 emit(instr); | 887 emit(instr); |
897 } | 888 } |
898 | 889 |
899 | 890 |
900 void Assembler::GenInstrRegister(Opcode opcode, | 891 void Assembler::GenInstrRegister(Opcode opcode, |
901 SecondaryField fmt, | 892 SecondaryField fmt, |
902 Register rt, | 893 Register rt, |
903 FPURegister fs, | 894 FPURegister fs, |
904 FPURegister fd, | 895 FPURegister fd, |
905 SecondaryField func) { | 896 SecondaryField func) { |
906 ASSERT(fd.is_valid() && fs.is_valid() && rt.is_valid()); | 897 ASSERT(fd.is_valid() && fs.is_valid() && rt.is_valid()); |
907 ASSERT(IsEnabled(FPU)); | |
908 Instr instr = opcode | fmt | (rt.code() << kRtShift) | 898 Instr instr = opcode | fmt | (rt.code() << kRtShift) |
909 | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func; | 899 | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func; |
910 emit(instr); | 900 emit(instr); |
911 } | 901 } |
912 | 902 |
913 | 903 |
914 void Assembler::GenInstrRegister(Opcode opcode, | 904 void Assembler::GenInstrRegister(Opcode opcode, |
915 SecondaryField fmt, | 905 SecondaryField fmt, |
916 Register rt, | 906 Register rt, |
917 FPUControlRegister fs, | 907 FPUControlRegister fs, |
918 SecondaryField func) { | 908 SecondaryField func) { |
919 ASSERT(fs.is_valid() && rt.is_valid()); | 909 ASSERT(fs.is_valid() && rt.is_valid()); |
920 ASSERT(IsEnabled(FPU)); | |
921 Instr instr = | 910 Instr instr = |
922 opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func; | 911 opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func; |
923 emit(instr); | 912 emit(instr); |
924 } | 913 } |
925 | 914 |
926 | 915 |
927 // Instructions with immediate value. | 916 // Instructions with immediate value. |
928 // Registers are in the order of the instruction encoding, from left to right. | 917 // Registers are in the order of the instruction encoding, from left to right. |
929 void Assembler::GenInstrImmediate(Opcode opcode, | 918 void Assembler::GenInstrImmediate(Opcode opcode, |
930 Register rs, | 919 Register rs, |
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945 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask); | 934 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask); |
946 emit(instr); | 935 emit(instr); |
947 } | 936 } |
948 | 937 |
949 | 938 |
950 void Assembler::GenInstrImmediate(Opcode opcode, | 939 void Assembler::GenInstrImmediate(Opcode opcode, |
951 Register rs, | 940 Register rs, |
952 FPURegister ft, | 941 FPURegister ft, |
953 int32_t j) { | 942 int32_t j) { |
954 ASSERT(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j))); | 943 ASSERT(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j))); |
955 ASSERT(IsEnabled(FPU)); | |
956 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) | 944 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) |
957 | (j & kImm16Mask); | 945 | (j & kImm16Mask); |
958 emit(instr); | 946 emit(instr); |
959 } | 947 } |
960 | 948 |
961 | 949 |
962 void Assembler::GenInstrJump(Opcode opcode, | 950 void Assembler::GenInstrJump(Opcode opcode, |
963 uint32_t address) { | 951 uint32_t address) { |
964 BlockTrampolinePoolScope block_trampoline_pool(this); | 952 BlockTrampolinePoolScope block_trampoline_pool(this); |
965 ASSERT(is_uint26(address)); | 953 ASSERT(is_uint26(address)); |
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1867 | 1855 |
1868 | 1856 |
1869 void Assembler::cvt_d_s(FPURegister fd, FPURegister fs) { | 1857 void Assembler::cvt_d_s(FPURegister fd, FPURegister fs) { |
1870 GenInstrRegister(COP1, S, f0, fs, fd, CVT_D_S); | 1858 GenInstrRegister(COP1, S, f0, fs, fd, CVT_D_S); |
1871 } | 1859 } |
1872 | 1860 |
1873 | 1861 |
1874 // Conditions. | 1862 // Conditions. |
1875 void Assembler::c(FPUCondition cond, SecondaryField fmt, | 1863 void Assembler::c(FPUCondition cond, SecondaryField fmt, |
1876 FPURegister fs, FPURegister ft, uint16_t cc) { | 1864 FPURegister fs, FPURegister ft, uint16_t cc) { |
1877 ASSERT(IsEnabled(FPU)); | |
1878 ASSERT(is_uint3(cc)); | 1865 ASSERT(is_uint3(cc)); |
1879 ASSERT((fmt & ~(31 << kRsShift)) == 0); | 1866 ASSERT((fmt & ~(31 << kRsShift)) == 0); |
1880 Instr instr = COP1 | fmt | ft.code() << 16 | fs.code() << kFsShift | 1867 Instr instr = COP1 | fmt | ft.code() << 16 | fs.code() << kFsShift |
1881 | cc << 8 | 3 << 4 | cond; | 1868 | cc << 8 | 3 << 4 | cond; |
1882 emit(instr); | 1869 emit(instr); |
1883 } | 1870 } |
1884 | 1871 |
1885 | 1872 |
1886 void Assembler::fcmp(FPURegister src1, const double src2, | 1873 void Assembler::fcmp(FPURegister src1, const double src2, |
1887 FPUCondition cond) { | 1874 FPUCondition cond) { |
1888 ASSERT(IsEnabled(FPU)); | |
1889 ASSERT(src2 == 0.0); | 1875 ASSERT(src2 == 0.0); |
1890 mtc1(zero_reg, f14); | 1876 mtc1(zero_reg, f14); |
1891 cvt_d_w(f14, f14); | 1877 cvt_d_w(f14, f14); |
1892 c(cond, D, src1, f14, 0); | 1878 c(cond, D, src1, f14, 0); |
1893 } | 1879 } |
1894 | 1880 |
1895 | 1881 |
1896 void Assembler::bc1f(int16_t offset, uint16_t cc) { | 1882 void Assembler::bc1f(int16_t offset, uint16_t cc) { |
1897 ASSERT(IsEnabled(FPU)); | |
1898 ASSERT(is_uint3(cc)); | 1883 ASSERT(is_uint3(cc)); |
1899 Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask); | 1884 Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask); |
1900 emit(instr); | 1885 emit(instr); |
1901 } | 1886 } |
1902 | 1887 |
1903 | 1888 |
1904 void Assembler::bc1t(int16_t offset, uint16_t cc) { | 1889 void Assembler::bc1t(int16_t offset, uint16_t cc) { |
1905 ASSERT(IsEnabled(FPU)); | |
1906 ASSERT(is_uint3(cc)); | 1890 ASSERT(is_uint3(cc)); |
1907 Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask); | 1891 Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask); |
1908 emit(instr); | 1892 emit(instr); |
1909 } | 1893 } |
1910 | 1894 |
1911 | 1895 |
1912 // Debugging. | 1896 // Debugging. |
1913 void Assembler::RecordJSReturn() { | 1897 void Assembler::RecordJSReturn() { |
1914 positions_recorder()->WriteRecordedPositions(); | 1898 positions_recorder()->WriteRecordedPositions(); |
1915 CheckBuffer(); | 1899 CheckBuffer(); |
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2298 } | 2282 } |
2299 | 2283 |
2300 if (patched) { | 2284 if (patched) { |
2301 CPU::FlushICache(pc+2, sizeof(Address)); | 2285 CPU::FlushICache(pc+2, sizeof(Address)); |
2302 } | 2286 } |
2303 } | 2287 } |
2304 | 2288 |
2305 } } // namespace v8::internal | 2289 } } // namespace v8::internal |
2306 | 2290 |
2307 #endif // V8_TARGET_ARCH_MIPS | 2291 #endif // V8_TARGET_ARCH_MIPS |
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