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1 | 1 |
2 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 2 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
3 // All Rights Reserved. | 3 // All Rights Reserved. |
4 // | 4 // |
5 // Redistribution and use in source and binary forms, with or without | 5 // Redistribution and use in source and binary forms, with or without |
6 // modification, are permitted provided that the following conditions are | 6 // modification, are permitted provided that the following conditions are |
7 // met: | 7 // met: |
8 // | 8 // |
9 // - Redistributions of source code must retain the above copyright notice, | 9 // - Redistributions of source code must retain the above copyright notice, |
10 // this list of conditions and the following disclaimer. | 10 // this list of conditions and the following disclaimer. |
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74 rm_ = rm; | 74 rm_ = rm; |
75 } | 75 } |
76 | 76 |
77 | 77 |
78 bool Operand::is_reg() const { | 78 bool Operand::is_reg() const { |
79 return rm_.is_valid(); | 79 return rm_.is_valid(); |
80 } | 80 } |
81 | 81 |
82 | 82 |
83 int Register::NumAllocatableRegisters() { | 83 int Register::NumAllocatableRegisters() { |
84 if (CpuFeatures::IsSupported(FPU)) { | |
85 return kMaxNumAllocatableRegisters; | 84 return kMaxNumAllocatableRegisters; |
86 } else { | |
87 return kMaxNumAllocatableRegisters - kGPRsPerNonFPUDouble; | |
88 } | |
89 } | 85 } |
90 | 86 |
91 | 87 |
92 int DoubleRegister::NumRegisters() { | 88 int DoubleRegister::NumRegisters() { |
93 if (CpuFeatures::IsSupported(FPU)) { | |
94 return FPURegister::kMaxNumRegisters; | 89 return FPURegister::kMaxNumRegisters; |
95 } else { | |
96 return 1; | |
97 } | |
98 } | 90 } |
99 | 91 |
100 | 92 |
101 int DoubleRegister::NumAllocatableRegisters() { | 93 int DoubleRegister::NumAllocatableRegisters() { |
102 if (CpuFeatures::IsSupported(FPU)) { | |
103 return FPURegister::kMaxNumAllocatableRegisters; | 94 return FPURegister::kMaxNumAllocatableRegisters; |
104 } else { | |
105 return 1; | |
106 } | |
107 } | 95 } |
108 | 96 |
109 | 97 |
110 int FPURegister::ToAllocationIndex(FPURegister reg) { | 98 int FPURegister::ToAllocationIndex(FPURegister reg) { |
111 ASSERT(reg.code() % 2 == 0); | 99 ASSERT(reg.code() % 2 == 0); |
112 ASSERT(reg.code() / 2 < kMaxNumAllocatableRegisters); | 100 ASSERT(reg.code() / 2 < kMaxNumAllocatableRegisters); |
113 ASSERT(reg.is_valid()); | 101 ASSERT(reg.is_valid()); |
114 ASSERT(!reg.is(kDoubleRegZero)); | 102 ASSERT(!reg.is(kDoubleRegZero)); |
115 ASSERT(!reg.is(kLithiumScratchDouble)); | 103 ASSERT(!reg.is(kLithiumScratchDouble)); |
116 return (reg.code() / 2); | 104 return (reg.code() / 2); |
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429 } | 417 } |
430 *reinterpret_cast<Instr*>(pc_) = x; | 418 *reinterpret_cast<Instr*>(pc_) = x; |
431 pc_ += kInstrSize; | 419 pc_ += kInstrSize; |
432 CheckTrampolinePoolQuick(); | 420 CheckTrampolinePoolQuick(); |
433 } | 421 } |
434 | 422 |
435 | 423 |
436 } } // namespace v8::internal | 424 } } // namespace v8::internal |
437 | 425 |
438 #endif // V8_MIPS_ASSEMBLER_MIPS_INL_H_ | 426 #endif // V8_MIPS_ASSEMBLER_MIPS_INL_H_ |
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