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| 1 /* | 1 /* |
| 2 * Copyright (c) 2015 Gurjant Kalsi <me@gurjantkalsi.com> | 2 * Copyright (c) 2015 Gurjant Kalsi <me@gurjantkalsi.com> |
| 3 * | 3 * |
| 4 * Permission is hereby granted, free of charge, to any person obtaining | 4 * Permission is hereby granted, free of charge, to any person obtaining |
| 5 * a copy of this software and associated documentation files | 5 * a copy of this software and associated documentation files |
| 6 * (the "Software"), to deal in the Software without restriction, | 6 * (the "Software"), to deal in the Software without restriction, |
| 7 * including without limitation the rights to use, copy, modify, merge, | 7 * including without limitation the rights to use, copy, modify, merge, |
| 8 * publish, distribute, sublicense, and/or sell copies of the Software, | 8 * publish, distribute, sublicense, and/or sell copies of the Software, |
| 9 * and to permit persons to whom the Software is furnished to do so, | 9 * and to permit persons to whom the Software is furnished to do so, |
| 10 * subject to the following conditions: | 10 * subject to the following conditions: |
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| 555 // block_addr is irrelevant when performing a bulk erase. | 555 // block_addr is irrelevant when performing a bulk erase. |
| 556 return ERR_INVALID_ARGS; | 556 return ERR_INVALID_ARGS; |
| 557 } | 557 } |
| 558 | 558 |
| 559 QSPI_CommandTypeDef erase_cmd; | 559 QSPI_CommandTypeDef erase_cmd; |
| 560 | 560 |
| 561 ssize_t num_erased_bytes; | 561 ssize_t num_erased_bytes; |
| 562 switch (instruction) { | 562 switch (instruction) { |
| 563 case SUBSECTOR_ERASE_CMD: { | 563 case SUBSECTOR_ERASE_CMD: { |
| 564 num_erased_bytes = N25QXXA_SUBSECTOR_SIZE; | 564 num_erased_bytes = N25QXXA_SUBSECTOR_SIZE; |
| 565 erase_cmd.AddressMode = get_address_size(block_addr); | 565 erase_cmd.AddressSize = get_address_size(block_addr); |
| 566 erase_cmd.Instruction = get_specialized_instruction(instruction, blo
ck_addr); | 566 erase_cmd.Instruction = get_specialized_instruction(instruction, blo
ck_addr); |
| 567 erase_cmd.AddressMode = QSPI_ADDRESS_1_LINE; |
| 568 erase_cmd.Address = block_addr; |
| 569 |
| 567 break; | 570 break; |
| 568 } | 571 } |
| 569 case SECTOR_ERASE_CMD: { | 572 case SECTOR_ERASE_CMD: { |
| 570 num_erased_bytes = N25QXXA_SECTOR_SIZE; | 573 num_erased_bytes = N25QXXA_SECTOR_SIZE; |
| 571 erase_cmd.AddressMode = get_address_size(block_addr); | 574 erase_cmd.AddressSize = get_address_size(block_addr); |
| 572 erase_cmd.Instruction = get_specialized_instruction(instruction, blo
ck_addr); | 575 erase_cmd.Instruction = get_specialized_instruction(instruction, blo
ck_addr); |
| 576 erase_cmd.AddressMode = QSPI_ADDRESS_1_LINE; |
| 577 erase_cmd.Address = block_addr; |
| 578 |
| 573 break; | 579 break; |
| 574 } | 580 } |
| 575 case BULK_ERASE_CMD: { | 581 case BULK_ERASE_CMD: { |
| 576 num_erased_bytes = device->total_size; | 582 num_erased_bytes = device->total_size; |
| 577 erase_cmd.AddressMode = QSPI_ADDRESS_NONE; | 583 erase_cmd.AddressMode = QSPI_ADDRESS_NONE; |
| 578 erase_cmd.Instruction = instruction; | 584 erase_cmd.Instruction = instruction; |
| 579 break; | 585 break; |
| 580 } | 586 } |
| 581 default: { | 587 default: { |
| 582 // Instruction must be a valid erase instruction. | 588 // Instruction must be a valid erase instruction. |
| 583 return ERR_INVALID_ARGS; | 589 return ERR_INVALID_ARGS; |
| 584 } | 590 } |
| 585 } | 591 } |
| 586 | 592 |
| 587 erase_cmd.InstructionMode = QSPI_INSTRUCTION_1_LINE; | 593 erase_cmd.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
| 588 erase_cmd.AddressSize = QSPI_ADDRESS_24_BITS; | |
| 589 erase_cmd.Address = block_addr; | |
| 590 erase_cmd.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; | 594 erase_cmd.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
| 591 erase_cmd.DataMode = QSPI_DATA_NONE; | 595 erase_cmd.DataMode = QSPI_DATA_NONE; |
| 592 erase_cmd.DummyCycles = 0; | 596 erase_cmd.DummyCycles = 0; |
| 593 erase_cmd.DdrMode = QSPI_DDR_MODE_DISABLE; | 597 erase_cmd.DdrMode = QSPI_DDR_MODE_DISABLE; |
| 594 erase_cmd.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; | 598 erase_cmd.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
| 595 erase_cmd.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; | 599 erase_cmd.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
| 596 | 600 |
| 597 | 601 |
| 598 /* Enable write operations */ | 602 /* Enable write operations */ |
| 599 status_t qspi_write_enable_result = qspi_write_enable_unsafe(&qspi_handle); | 603 status_t qspi_write_enable_result = qspi_write_enable_unsafe(&qspi_handle); |
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| 801 HAL_StatusTypeDef hal_result = HAL_QSPI_MemoryMapped(&qspi_handle, &s_comman
d, &linear_mode_cfg); | 805 HAL_StatusTypeDef hal_result = HAL_QSPI_MemoryMapped(&qspi_handle, &s_comman
d, &linear_mode_cfg); |
| 802 if (hal_result != HAL_OK) { | 806 if (hal_result != HAL_OK) { |
| 803 result = hal_error_to_status(hal_result); | 807 result = hal_error_to_status(hal_result); |
| 804 goto err; | 808 goto err; |
| 805 } | 809 } |
| 806 | 810 |
| 807 err: | 811 err: |
| 808 mutex_release(&spiflash_mutex); | 812 mutex_release(&spiflash_mutex); |
| 809 return result; | 813 return result; |
| 810 } | 814 } |
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