[turbofan] Use cmn on ARM64 for negated rhs cmp

test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "test/unittests/compiler/instruction-selector-unittest.h"
 
 namespace v8 {
 namespace internal {
 namespace compiler {
 
@@ skipping 2515 matching lines @@
     EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
     ASSERT_EQ(2U, s[0]->InputCount());
     EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
     EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
     EXPECT_EQ(1U, s[0]->OutputCount());
     EXPECT_EQ(kFlags_set, s[0]->flags_mode());
     EXPECT_EQ(kNotEqual, s[0]->flags_condition());
   }
 }
 
+namespace {
+
+struct IntegerCmp {
+  MachInst2 mi;
+  FlagsCondition cond;
+};
+
+
+std::ostream& operator<<(std::ostream& os, const IntegerCmp& cmp) {
+  return os << cmp.mi;
+}
+
+
+// ARM64 32-bit integer comparison instructions.
+const IntegerCmp kIntegerCmpInstructions[] = {
+    {{&RawMachineAssembler::Word32Equal, "Word32Equal", kArm64Cmp32,
+      kMachInt32},
+     kEqual},
+    {{&RawMachineAssembler::Int32LessThan, "Int32LessThan", kArm64Cmp32,
+      kMachInt32},
+     kSignedLessThan},
+    {{&RawMachineAssembler::Int32LessThanOrEqual, "Int32LessThanOrEqual",
+      kArm64Cmp32, kMachInt32},
+     kSignedLessThanOrEqual},
+    {{&RawMachineAssembler::Uint32LessThan, "Uint32LessThan", kArm64Cmp32,
+      kMachUint32},
+     kUnsignedLessThan},
+    {{&RawMachineAssembler::Uint32LessThanOrEqual, "Uint32LessThanOrEqual",
+      kArm64Cmp32, kMachUint32},
+     kUnsignedLessThanOrEqual}};
+
+}  // namespace
+
+
+TEST_F(InstructionSelectorTest, Word32CompareNegateWithWord32Shift) {
+  TRACED_FOREACH(IntegerCmp, cmp, kIntegerCmpInstructions) {
+    TRACED_FOREACH(Shift, shift, kShiftInstructions) {
+      // Test 32-bit operations. Ignore ROR shifts, as compare-negate does not
+      // support them.
+      if (shift.mi.machine_type != kMachInt32 ||
+          shift.mi.arch_opcode == kArm64Ror32) {
+        continue;
+      }
+
+      TRACED_FORRANGE(int32_t, imm, -32, 63) {
+        StreamBuilder m(this, kMachInt32, kMachInt32, kMachInt32);
+        Node* const p0 = m.Parameter(0);
+        Node* const p1 = m.Parameter(1);
+        Node* r = (m.*shift.mi.constructor)(p1, m.Int32Constant(imm));
+        m.Return(
+            (m.*cmp.mi.constructor)(p0, m.Int32Sub(m.Int32Constant(0), r)));
+        Stream s = m.Build();
+        ASSERT_EQ(1U, s.size());
+        EXPECT_EQ(kArm64Cmn32, s[0]->arch_opcode());
+        EXPECT_EQ(3U, s[0]->InputCount());
+        EXPECT_EQ(shift.mode, s[0]->addressing_mode());
+        EXPECT_EQ(imm, s.ToInt32(s[0]->InputAt(2)));
+        EXPECT_EQ(1U, s[0]->OutputCount());
+        EXPECT_EQ(kFlags_set, s[0]->flags_mode());
+        EXPECT_EQ(cmp.cond, s[0]->flags_condition());
+      }
+    }
+  }
+}
+
 
 // -----------------------------------------------------------------------------
 // Miscellaneous
 
 
 static const MachInst2 kLogicalWithNotRHSs[] = {
     {&RawMachineAssembler::Word32And, "Word32And", kArm64Bic32, kMachInt32},
     {&RawMachineAssembler::Word64And, "Word64And", kArm64Bic, kMachInt64},
     {&RawMachineAssembler::Word32Or, "Word32Or", kArm64Orn32, kMachInt32},
     {&RawMachineAssembler::Word64Or, "Word64Or", kArm64Orn, kMachInt64},
@@ skipping 636 matching lines @@
   ASSERT_EQ(2U, s[0]->InputCount());
   EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
   EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
   ASSERT_EQ(1U, s[0]->OutputCount());
   EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8