Subzero. ARM32. Refactors atomic intrinsics lowering.

tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

 ; This tests each of the supported NaCl atomic instructions for every
 ; size allowed.
 
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck --check-prefix=O2 %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 
@@ skipping 228 matching lines @@
   call void @llvm.nacl.atomic.store.i64(i64 12345678901234, i64* %ptr, i32 6)
   ret void
 }
 ; CHECK-LABEL: test_atomic_store_64_const
 ; CHECK: mov {{.*}},0x73ce2ff2
 ; CHECK: mov {{.*}},0xb3a
 ; CHECK: movq x{{.*}},QWORD
 ; CHECK: movq QWORD {{.*}},x{{.*}}
 ; CHECK: mfence
 ; ARM32-LABEL: test_atomic_store_64_const
-; ARM32: dmb
 ; ARM32: movw [[T0:r[0-9]+]], #12274
 ; ARM32: movt [[T0]], #29646
 ; ARM32: movw r{{[0-9]+}}, #2874
+; ARM32: dmb
 ; ARM32: .L[[RETRY:.*]]:
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [[MEM:.*]]
 ; ARM32: strexd [[S:r[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}}, [[MEM]]
 ; ARM32: cmp [[S]], #0
 ; ARM32: bne .L[[RETRY]]
 ; ARM32: dmb
 
 ;;; RMW
 
 ;; add
@@ skipping 72 matching lines @@
 ; CHECK: adc ecx,{{.*e.[^x]}}
 ; Ptr cannot be eax, ebx, ecx, or edx (used up for the expected and desired).
 ; It can be esi, edi, or ebp though, for example (so we need to be careful
 ; about rejecting eb* and ed*.)
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
 ; CHECK: jne [[LABEL]]
 ; ARM32-LABEL: test_atomic_rmw_add_64
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: adds
-; ARM32-NEXT: adc
+; ARM32: adc
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 
 ; Same test as above, but with a global address to test FakeUse issues.
 define internal i64 @test_atomic_rmw_add_64_global(i64 %v) {
 entry:
   %ptr = bitcast [8 x i8]* @SzGlobal64 to i64*
   %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6)
   ret i64 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_add_64_global
 ; ARM32-LABEL: test_atomic_rmw_add_64_global
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: adds
-; ARM32-NEXT: adc
+; ARM32: adc
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 
 ; Test with some more register pressure. When we have an alloca, ebp is
 ; used to manage the stack frame, so it cannot be used as a register either.
 declare void @use_ptr(i32 %iptr)
 
 define internal i64 @test_atomic_rmw_add_64_alloca(i32 %iptr, i64 %v) {
 entry:
@@ skipping 20 matching lines @@
 ; It also cannot be ebp since we use that for alloca. Also make sure it's
 ; not esp, since that's the stack pointer and mucking with it will break
 ; the later use_ptr function call.
 ; That pretty much leaves esi, or edi as the only viable registers.
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{[ds]}}i]
 ; CHECK: call {{.*}} R_{{.*}} use_ptr
 ; ARM32-LABEL: test_atomic_rmw_add_64_alloca
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: adds
-; ARM32-NEXT: adc
+; ARM32: adc
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_rmw_add_32_ignored(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 %v, i32 6)
   ret i32 %v
 }
@@ skipping 36 matching lines @@
 ; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
 ; CHECK: add ebx,{{.*e.[^x]}}
 ; CHECK: mov ecx,edx
 ; CHECK: adc ecx,{{.*e.[^x]}}
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
 ; CHECK: jne [[LABEL]]
 ; ARM32-LABEL: test_atomic_rmw_add_64_loop
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: adds
-; ARM32-NEXT: adc
+; ARM32: adc
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 ; ARM32: b
 
 ;; sub
 
 define internal i32 @test_atomic_rmw_sub_8(i32 %iptr, i32 %v) {
 entry:
   %trunc = trunc i32 %v to i8
@@ skipping 65 matching lines @@
 ; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
 ; CHECK: sub ebx,{{.*e.[^x]}}
 ; CHECK: mov ecx,edx
 ; CHECK: sbb ecx,{{.*e.[^x]}}
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
 ; CHECK: jne [[LABEL]]
 ; ARM32-LABEL: test_atomic_rmw_sub_64
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: subs
-; ARM32-NEXT: sbc
+; ARM32: sbc
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_rmw_sub_32_ignored(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 2, i32* %ptr, i32 %v, i32 6)
   ret i32 %v
 }
@@ skipping 38 matching lines @@
 define internal i32 @test_atomic_rmw_or_8_global(i32 %v) {
 entry:
   %trunc = trunc i32 %v to i8
   %ptr = bitcast [1 x i8]* @SzGlobal8 to i8*
   %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 3, i8* %ptr, i8 %trunc, i32 6)
   %a_ext = zext i8 %a to i32
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_or_8_global
 ; ARM32-LABEL: test_atomic_rmw_or_8_global
+; ARM32: dmb
 ; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal8
 ; ARM32: movt [[PTR]], #:upper16:SzGlobal8
-; ARM32: dmb
 ; ARM32: ldrexb r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
 ; ARM32: orr
 ; ARM32: strexb
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
 entry:
   %trunc = trunc i32 %v to i16
   %ptr = inttoptr i32 %iptr to i16*
@@ skipping 18 matching lines @@
 define internal i32 @test_atomic_rmw_or_16_global(i32 %v) {
 entry:
   %trunc = trunc i32 %v to i16
   %ptr = bitcast [2 x i8]* @SzGlobal16 to i16*
   %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 3, i16* %ptr, i16 %trunc, i32 6)
   %a_ext = zext i16 %a to i32
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_or_16_global
 ; ARM32-LABEL: test_atomic_rmw_or_16_global
+; ARM32: dmb
 ; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal16
 ; ARM32: movt [[PTR]], #:upper16:SzGlobal16
-; ARM32: dmb
 ; ARM32: ldrexh r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
 ; ARM32: orr
 ; ARM32: strexh
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
@@ skipping 14 matching lines @@
 
 ; Same test as above, but with a global address to test FakeUse issues.
 define internal i32 @test_atomic_rmw_or_32_global(i32 %v) {
 entry:
   %ptr = bitcast [4 x i8]* @SzGlobal32 to i32*
   %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
   ret i32 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_or_32_global
 ; ARM32-LABEL: test_atomic_rmw_or_32_global
+; ARM32: dmb
 ; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal32
 ; ARM32: movt [[PTR]], #:upper16:SzGlobal32
-; ARM32: dmb
 ; ARM32: ldrex r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
 ; ARM32: orr
 ; ARM32: strex
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 3, i64* %ptr, i64 %v, i32 6)
   ret i64 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_or_64
 ; CHECK: push ebx
 ; CHECK: mov eax,DWORD PTR [{{.*}}]
 ; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
 ; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
 ; CHECK: or ebx,{{.*e.[^x]}}
 ; CHECK: mov ecx,edx
 ; CHECK: or ecx,{{.*e.[^x]}}
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
 ; CHECK: jne [[LABEL]]
 ; ARM32-LABEL: test_atomic_rmw_or_64
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: orr
-; ARM32-NEXT: orr
+; ARM32: orr
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_rmw_or_32_ignored(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
   ret i32 %v
 }
@@ skipping 89 matching lines @@
 ; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
 ; CHECK: and ebx,{{.*e.[^x]}}
 ; CHECK: mov ecx,edx
 ; CHECK: and ecx,{{.*e.[^x]}}
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
 ; CHECK: jne [[LABEL]]
 ; ARM32-LABEL: test_atomic_rmw_and_64
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: and
-; ARM32-NEXT: and
+; ARM32: and
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_rmw_and_32_ignored(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 4, i32* %ptr, i32 %v, i32 6)
   ret i32 %v
 }
@@ skipping 87 matching lines @@
 ; CHECK: mov ebx,eax
 ; CHECK: or ebx,{{.*e.[^x]}}
 ; CHECK: mov ecx,edx
 ; CHECK: or ecx,{{.*e.[^x]}}
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
 ; CHECK: jne
 ; ARM32-LABEL: test_atomic_rmw_xor_64
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: eor
-; ARM32-NEXT: eor
+; ARM32: eor
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_rmw_xor_32_ignored(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32* %ptr, i32 %v, i32 6)
   ret i32 %v
 }
@@ skipping 119 matching lines @@
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_8
 ; CHECK: mov eax,{{.*}}
 ; Need to check that eax isn't used as the address register or the desired.
 ; since it is already used as the *expected* register.
 ; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],{{[^a]}}l
 ; ARM32-LABEL: test_atomic_cmpxchg_8
 ; ARM32: dmb
 ; ARM32: ldrexb
 ; ARM32: cmp
+; ARM32: {{strb|mov}}
 ; ARM32: strexbeq
-; ARM32: {{strb|mov}}ne
 ; ARM32: cmpeq
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected,
                                             i32 %desired) {
 entry:
   %trunc_exp = trunc i32 %expected to i16
   %trunc_des = trunc i32 %desired to i16
   %ptr = inttoptr i32 %iptr to i16*
   %old = call i16 @llvm.nacl.atomic.cmpxchg.i16(i16* %ptr, i16 %trunc_exp,
                                                i16 %trunc_des, i32 6, i32 6)
   %old_ext = zext i16 %old to i32
   ret i32 %old_ext
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_16
 ; CHECK: mov {{ax|eax}},{{.*}}
 ; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}],{{[^a]}}x
 ; ARM32-LABEL: test_atomic_cmpxchg_16
 ; ARM32: dmb
 ; ARM32: ldrexh
 ; ARM32: cmp
+; ARM32: {{strh|mov}}
 ; ARM32: strexheq
-; ARM32: {{strh|mov}}ne
 ; ARM32: cmpeq
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected,
                                             i32 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
                                                i32 %desired, i32 6, i32 6)
   ret i32 %old
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_32
 ; CHECK: mov eax,{{.*}}
 ; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
 ; ARM32-LABEL: test_atomic_cmpxchg_32
 ; ARM32: dmb
 ; ARM32: ldrex
 ; ARM32: cmp
+; ARM32: {{str|mov}}
 ; ARM32: strexeq
-; ARM32: {{str|mov}}ne
 ; ARM32: cmpeq
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected,
                                             i64 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
                                                i64 %desired, i32 6, i32 6)
   ret i64 %old
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_64
 ; CHECK: push ebx
 ; CHECK-DAG: mov edx
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
 ; edx and eax are already the return registers, so they don't actually
 ; need to be reshuffled via movs. The next test stores the result
 ; somewhere, so in that case they do need to be mov'ed.
 ; ARM32-LABEL: test_atomic_cmpxchg_64
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
 ; ARM32: cmp
-; ARM32-NEXT: cmpeq
+; ARM32: cmpeq
+; ARM32: mov
+; ARM32: mov
 ; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32: {{str|mov}}ne
-; ARM32: {{str|mov}}ne
 ; ARM32: cmpeq
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i64 @test_atomic_cmpxchg_64_undef(i32 %iptr, i64 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 undef,
                                                i64 %desired, i32 6, i32 6)
   ret i64 %old
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_64_undef
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
 ; ARM32-LABEL: test_atomic_cmpxchg_64_undef
 ; ARM32: mov r{{[0-9]+}}, #0
 ; ARM32: mov r{{[0-9]+}}, #0
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
 ; ARM32: cmp
-; ARM32-NEXT: cmpeq
+; ARM32: cmpeq
+; ARM32: mov
+; ARM32: mov
 ; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32: {{str|mov}}ne
-; ARM32: {{str|mov}}ne
 ; ARM32: cmpeq
 ; ARM32: bne
 ; ARM32: dmb
 
 ; Test a case where %old really does need to be copied out of edx:eax.
 define internal void @test_atomic_cmpxchg_64_store(
     i32 %ret_iptr, i32 %iptr, i64 %expected, i64 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
                                                 i64 %desired, i32 6, i32 6)
   %__6 = inttoptr i32 %ret_iptr to i64*
   store i64 %old, i64* %__6, align 1
   ret void
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_64_store
 ; CHECK: push ebx
 ; CHECK-DAG: mov edx
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
 ; CHECK-DAG: mov {{.*}},edx
 ; CHECK-DAG: mov {{.*}},eax
 ; ARM32-LABEL: test_atomic_cmpxchg_64_store
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
 ; ARM32: cmp
-; ARM32-NEXT: cmpeq
+; ARM32: cmpeq
+; ARM32: mov
+; ARM32: mov
 ; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32: {{str|mov}}ne
-; ARM32: {{str|mov}}ne
 ; ARM32: cmpeq
 ; ARM32: bne
 ; ARM32: dmb
 ; ARM32: str
 ; ARM32: str
 
 ; Test with some more register pressure. When we have an alloca, ebp is
 ; used to manage the stack frame, so it cannot be used as a register either.
 define internal i64 @test_atomic_cmpxchg_64_alloca(i32 %iptr, i64 %expected,
                                                    i64 %desired) {
@@ skipping 22 matching lines @@
 ; It also cannot be ebp since we use that for alloca. Also make sure it's
 ; not esp, since that's the stack pointer and mucking with it will break
 ; the later use_ptr function call.
 ; That pretty much leaves esi, or edi as the only viable registers.
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{[ds]}}i]
 ; CHECK: call {{.*}} R_{{.*}} use_ptr
 ; ARM32-LABEL: test_atomic_cmpxchg_64_alloca
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
 ; ARM32: cmp
-; ARM32-NEXT: cmpeq
+; ARM32: cmpeq
+; ARM32: mov
+; ARM32: mov
 ; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32: {{str|mov}}ne
-; ARM32: {{str|mov}}ne
 ; ARM32: cmpeq
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_cmpxchg_32_ignored(i32 %iptr, i32 %expected,
                                                     i32 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
                                                     i32 %desired, i32 6, i32 6)
   ret i32 0
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_32_ignored
 ; CHECK: mov eax,{{.*}}
 ; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
 ; ARM32-LABEL: test_atomic_cmpxchg_32_ignored
 ; ARM32: dmb
 ; ARM32: ldrex
 ; ARM32: cmp
 ; ARM32: strexeq
-; ARM32: {{str|mov}}ne
 ; ARM32: cmpeq
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i64 @test_atomic_cmpxchg_64_ignored(i32 %iptr, i64 %expected,
                                                     i64 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %ignored = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
                                                     i64 %desired, i32 6, i32 6)
@@ skipping 185 matching lines @@
   br i1 %cmp, label %done, label %body
 done:
   ret void
 }
 ; O2-LABEL: test_cmpxchg8b_regalloc
 ;;; eax and some other register will be used in the cmpxchg instruction.
 ; O2: lock cmpxchg8b QWORD PTR
 ;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable.
 ; O2-NOT: {{eax|ecx|edx|ebx}}
 ; O2: pop ebx