Subzero. ARM32. Refactors atomic intrinsics lowering.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 228 matching lines @@
   };
 
   CondWhenTrue lowerFcmpCond(const InstFcmp *Instr);
   void lowerFcmp(const InstFcmp *Instr) override;
   CondWhenTrue lowerInt8AndInt16IcmpCond(InstIcmp::ICond Condition,
                                          Operand *Src0, Operand *Src1);
   CondWhenTrue lowerInt32IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
                                   Operand *Src1);
   CondWhenTrue lowerInt64IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
                                   Operand *Src1);
+  CondWhenTrue lowerIcmpCond(InstIcmp::ICond Condition, Operand *Src0,
+                             Operand *Src1);
   CondWhenTrue lowerIcmpCond(const InstIcmp *Instr);
   void lowerIcmp(const InstIcmp *Instr) override;
+  /// Emits the basic sequence for lower-linked/store-exclusive loops:
+  ///
+  /// retry:
+  ///        ldrex tmp, [Addr]
+  ///        StoreValue = Operation(tmp)
+  ///        strexCond success, StoreValue, [Addr]
+  ///        cmpCond success, #0
+  ///        bne retry
+  ///
+  /// Operation needs to return which value to strex in Addr, it must not change
+  /// the flags if Cond is not AL, and must not emit any instructions that could
+  /// end up writting to memory. Operation also needs to handle fake-defing for

[Jim Stichnoth, 2016/02/17 03:50:17]

writing

[John, 2016/02/17 13:01:39]

Done.

+  /// i64 handling.
+  void
+  lowerLoadLinkedStoreExclusive(Type Ty, Operand *Addr,
+                                std::function<Variable *(Variable *)> Operation,
+                                CondARM32::Cond Cond = CondARM32::AL);
+  void lowerInt64AtomicRMW(Variable *Dest, uint32_t Operation, Operand *Ptr,
+                           Operand *Val);
   void lowerAtomicRMW(Variable *Dest, uint32_t Operation, Operand *Ptr,
                       Operand *Val);
   void lowerIntrinsicCall(const InstIntrinsicCall *Instr) override;
   void lowerInsertElement(const InstInsertElement *Instr) override;
   void lowerLoad(const InstLoad *Instr) override;
   void lowerPhi(const InstPhi *Instr) override;
   void lowerRet(const InstRet *Instr) override;
   void lowerSelect(const InstSelect *Instr) override;
   void lowerStore(const InstStore *Instr) override;
   void lowerSwitch(const InstSwitch *Instr) override;
@@ skipping 92 matching lines @@
     Context.insert<InstARM32Eor>(Dest, Src0, Src1, Pred);
   }
   /// _ldr, for all your memory to Variable data moves. It handles all types
   /// (integer, floating point, and vectors.) Addr needs to be valid for Dest's
   /// type (e.g., no immediates for vector loads, and no index registers for fp
   /// loads.)
   void _ldr(Variable *Dest, OperandARM32Mem *Addr,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Ldr>(Dest, Addr, Pred);
   }
-  void _ldrex(Variable *Dest, OperandARM32Mem *Addr,
-              CondARM32::Cond Pred = CondARM32::AL) {
-    Context.insert<InstARM32Ldrex>(Dest, Addr, Pred);
+  InstARM32Ldrex *_ldrex(Variable *Dest, OperandARM32Mem *Addr,
+                         CondARM32::Cond Pred = CondARM32::AL) {
+    auto *Ldrex = Context.insert<InstARM32Ldrex>(Dest, Addr, Pred);
     if (auto *Dest64 = llvm::dyn_cast<Variable64On32>(Dest)) {
       Context.insert<InstFakeDef>(Dest64->getLo(), Dest);
       Context.insert<InstFakeDef>(Dest64->getHi(), Dest);
     }
+    return Ldrex;
   }
   void _lsl(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Lsl>(Dest, Src0, Src1, Pred);
   }
   void _lsls(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     constexpr bool SetFlags = true;
     Context.insert<InstARM32Lsl>(Dest, Src0, Src1, Pred, SetFlags);
   }
@@ skipping 905 matching lines @@
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H