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Issue 1407613002: Add "add immediate" instruction to the ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix issues in patch set 2. Created 5 years, 2 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 // 4 //
5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
6 // Please update the (git) revision if we merge changes from Dart. 6 // Please update the (git) revision if we merge changes from Dart.
7 // https://code.google.com/p/dart/wiki/GettingTheSource 7 // https://code.google.com/p/dart/wiki/GettingTheSource
8 8
9 #ifndef VM_ASSEMBLER_ARM_H_ 9 #ifndef VM_ASSEMBLER_ARM_H_
10 #define VM_ASSEMBLER_ARM_H_ 10 #define VM_ASSEMBLER_ARM_H_
(...skipping 122 matching lines...)
133 } 133 }
134 134
135 // Data-processing operands - Immediate. 135 // Data-processing operands - Immediate.
136 explicit Operand(uint32_t immediate) { 136 explicit Operand(uint32_t immediate) {
137 ASSERT(immediate < (1 << kImmed8Bits)); 137 ASSERT(immediate < (1 << kImmed8Bits));
138 type_ = 1; 138 type_ = 1;
139 encoding_ = immediate; 139 encoding_ = immediate;
140 } 140 }
141 141
142 #if 0 142 #if 0
143 // Moved to AssemblerARM32::encodeImm12FromFlexImm. 143 // Moved to decode in IceAssemblerARM32.cpp
144 // Data-processing operands - Rotated immediate. 144 // Data-processing operands - Rotated immediate.
145 Operand(uint32_t rotate, uint32_t immed8) { 145 Operand(uint32_t rotate, uint32_t immed8) {
146 ASSERT((rotate < (1 << kRotateBits)) && (immed8 < (1 << kImmed8Bits))); 146 ASSERT((rotate < (1 << kRotateBits)) && (immed8 < (1 << kImmed8Bits)));
147 type_ = 1; 147 type_ = 1;
148 encoding_ = (rotate << kRotateShift) | (immed8 << kImmed8Shift); 148 encoding_ = (rotate << kRotateShift) | (immed8 << kImmed8Shift);
149 } 149 }
150 #endif 150 #endif
151 151
152 #if 0
153 // Moved to decode in IceAssemblerARM32.cpp
152 // Data-processing operands - Register. 154 // Data-processing operands - Register.
153 explicit Operand(Register rm) { 155 explicit Operand(Register rm) {
154 type_ = 0; 156 type_ = 0;
155 encoding_ = static_cast<uint32_t>(rm); 157 encoding_ = static_cast<uint32_t>(rm);
156 } 158 }
159 #endif
157 160
158 // Data-processing operands - Logical shift/rotate by immediate. 161 // Data-processing operands - Logical shift/rotate by immediate.
159 Operand(Register rm, Shift shift, uint32_t shift_imm) { 162 Operand(Register rm, Shift shift, uint32_t shift_imm) {
160 ASSERT(shift_imm < (1 << kShiftImmBits)); 163 ASSERT(shift_imm < (1 << kShiftImmBits));
161 type_ = 0; 164 type_ = 0;
162 encoding_ = shift_imm << kShiftImmShift | 165 encoding_ = shift_imm << kShiftImmShift |
163 static_cast<uint32_t>(shift) << kShiftShift | 166 static_cast<uint32_t>(shift) << kShiftShift |
164 static_cast<uint32_t>(rm); 167 static_cast<uint32_t>(rm);
165 } 168 }
166 169
(...skipping 269 matching lines...)
436 void and_(Register rd, Register rn, Operand o, Condition cond = AL); 439 void and_(Register rd, Register rn, Operand o, Condition cond = AL);
437 440
438 void eor(Register rd, Register rn, Operand o, Condition cond = AL); 441 void eor(Register rd, Register rn, Operand o, Condition cond = AL);
439 442
440 void sub(Register rd, Register rn, Operand o, Condition cond = AL); 443 void sub(Register rd, Register rn, Operand o, Condition cond = AL);
441 void subs(Register rd, Register rn, Operand o, Condition cond = AL); 444 void subs(Register rd, Register rn, Operand o, Condition cond = AL);
442 445
443 void rsb(Register rd, Register rn, Operand o, Condition cond = AL); 446 void rsb(Register rd, Register rn, Operand o, Condition cond = AL);
444 void rsbs(Register rd, Register rn, Operand o, Condition cond = AL); 447 void rsbs(Register rd, Register rn, Operand o, Condition cond = AL);
445 448
449 #if 0
450 // Moved to IceAssemblerARM32::mov
446 void add(Register rd, Register rn, Operand o, Condition cond = AL); 451 void add(Register rd, Register rn, Operand o, Condition cond = AL);
447 452
448 void adds(Register rd, Register rn, Operand o, Condition cond = AL); 453 void adds(Register rd, Register rn, Operand o, Condition cond = AL);
454 #endif
449 455
450 void adc(Register rd, Register rn, Operand o, Condition cond = AL); 456 void adc(Register rd, Register rn, Operand o, Condition cond = AL);
451 457
452 void adcs(Register rd, Register rn, Operand o, Condition cond = AL); 458 void adcs(Register rd, Register rn, Operand o, Condition cond = AL);
453 459
454 void sbc(Register rd, Register rn, Operand o, Condition cond = AL); 460 void sbc(Register rd, Register rn, Operand o, Condition cond = AL);
455 461
456 void sbcs(Register rd, Register rn, Operand o, Condition cond = AL); 462 void sbcs(Register rd, Register rn, Operand o, Condition cond = AL);
457 463
458 void rsc(Register rd, Register rn, Operand o, Condition cond = AL); 464 void rsc(Register rd, Register rn, Operand o, Condition cond = AL);
459 465
460 void tst(Register rn, Operand o, Condition cond = AL); 466 void tst(Register rn, Operand o, Condition cond = AL);
461 467
462 void teq(Register rn, Operand o, Condition cond = AL); 468 void teq(Register rn, Operand o, Condition cond = AL);
463 469
464 void cmp(Register rn, Operand o, Condition cond = AL); 470 void cmp(Register rn, Operand o, Condition cond = AL);
465 471
466 void cmn(Register rn, Operand o, Condition cond = AL); 472 void cmn(Register rn, Operand o, Condition cond = AL);
467 473
468 void orr(Register rd, Register rn, Operand o, Condition cond = AL); 474 void orr(Register rd, Register rn, Operand o, Condition cond = AL);
469 void orrs(Register rd, Register rn, Operand o, Condition cond = AL); 475 void orrs(Register rd, Register rn, Operand o, Condition cond = AL);
470 476
471 #if 0 477 #if 0
472 // Moved to IceAssemblerARM32::mov(..FlexImm..) 478 // Moved to IceAssemblerARM32::mov
473 // TODO(kschimpf) other forms of move.
474 void mov(Register rd, Operand o, Condition cond = AL); 479 void mov(Register rd, Operand o, Condition cond = AL);
480 void movs(Register rd, Operand o, Condition cond = AL);
475 #endif 481 #endif
476 void movs(Register rd, Operand o, Condition cond = AL);
477 482
478 void bic(Register rd, Register rn, Operand o, Condition cond = AL); 483 void bic(Register rd, Register rn, Operand o, Condition cond = AL);
479 void bics(Register rd, Register rn, Operand o, Condition cond = AL); 484 void bics(Register rd, Register rn, Operand o, Condition cond = AL);
480 485
481 void mvn(Register rd, Operand o, Condition cond = AL); 486 void mvn(Register rd, Operand o, Condition cond = AL);
482 void mvns(Register rd, Operand o, Condition cond = AL); 487 void mvns(Register rd, Operand o, Condition cond = AL);
483 488
484 // Miscellaneous data-processing instructions. 489 // Miscellaneous data-processing instructions.
485 void clz(Register rd, Register rm, Condition cond = AL); 490 void clz(Register rd, Register rm, Condition cond = AL);
486 491
(...skipping 735 matching lines...)
1222 Register new_value, 1227 Register new_value,
1223 FieldContent old_content); 1228 FieldContent old_content);
1224 1229
1225 DISALLOW_ALLOCATION(); 1230 DISALLOW_ALLOCATION();
1226 DISALLOW_COPY_AND_ASSIGN(Assembler); 1231 DISALLOW_COPY_AND_ASSIGN(Assembler);
1227 }; 1232 };
1228 1233
1229 } // namespace dart 1234 } // namespace dart
1230 1235
1231 #endif // VM_ASSEMBLER_ARM_H_ 1236 #endif // VM_ASSEMBLER_ARM_H_
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