Supports FrameLookup vm test on MIPS

runtime/vm/assembler_mips.h

Index: runtime/vm/assembler_mips.h
===================================================================
--- runtime/vm/assembler_mips.h	(revision 21219)
+++ runtime/vm/assembler_mips.h	(working copy)
@@ -169,8 +169,8 @@
 
   // Set up a stub frame so that the stack traversal code can easily identify
   // a stub frame.
-  void EnterStubFrame();
-  void LeaveStubFrame();
+  void EnterStubFrame(bool uses_pp = false);
+  void LeaveStubFrame(bool uses_pp = false);
 
   // Instruction pattern from entrypoint is used in dart frame prologs
   // to set up the frame and save a PC which can be used to figure out the
@@ -565,6 +565,24 @@
     }
   }
 
+  void AddImmediate(Register rd, int32_t value) {
+    if (Utils::IsInt(kImmBits, value)) {
+      addiu(rd, rd, Immediate(value));
+    } else {
+      LoadImmediate(TMP1, value);
+      addu(rd, rd, TMP1);
+    }

[regis, 2013/04/10 20:53:00]

You could forward to AddImmediate(rd, rd, value).

[zra, 2013/04/10 21:59:05]

Done.

+  }
+
+  void AddImmediate(Register rd, Register rs, int32_t value) {
+    if (Utils::IsInt(kImmBits, value)) {
+      addiu(rd, rs, Immediate(value));
+    } else {
+      LoadImmediate(TMP1, value);
+      addu(rd, rs, TMP1);
+    }
+  }
+
   void BranchEqual(Register rd, int32_t value, Label* l) {
     LoadImmediate(TMP1, value);
     beq(rd, TMP1, l);
@@ -677,8 +695,12 @@
   void LoadObject(Register rd, const Object& object);
   void PushObject(const Object& object);
 
+  // Branch if a comparison with a result already in rd satisfies the
+  // Condition c.
+  void BranchOnCondition(Register rd, Label* l, Condition c);

[regis, 2013/04/10 20:53:00]

It would be more natural to have the condition as first parameter, as on Intel
(or maybe second?). It is last on ARM, because each instruction is conditional
and we want the condition to default to 'always', without passing it explicitly.
You could also use the shorter name 'Branch'. Up to you.
But more importantly, why do you need this? It seems that it will map to one
instruction anyway. I would prefer to see the real code being generated, rather
than making it look closer to the ARM version.
If the purpose is to emulate the branch on condition of the flow graph, maybe T8
should be implicit?
You already have BranchEqual, etc... this is getting confusing. Let's chat.

+
   // Sets register rd to zero if the object is equal to register rn,
-  // set to non-zero otherwise.
+  // sets it to non-zero otherwise.
   void CompareObject(Register rd, Register rn, const Object& object);
 
   void LoadClassId(Register result, Register object);