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Side by Side Diff: runtime/vm/assembler_arm.cc

Issue 1407393006: Make arm assembler explicitly take both registers for load/store-pair. (Closed) Base URL: git@github.com:dart-lang/sdk.git@master
Patch Set: Created 5 years, 2 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // NOLINT 5 #include "vm/globals.h" // NOLINT
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/cpu.h" 9 #include "vm/cpu.h"
10 #include "vm/longjump.h" 10 #include "vm/longjump.h"
(...skipping 475 matching lines...) Expand 10 before | Expand all | Expand 10 after
486 void Assembler::ldrsb(Register rd, Address ad, Condition cond) { 486 void Assembler::ldrsb(Register rd, Address ad, Condition cond) {
487 EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad); 487 EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad);
488 } 488 }
489 489
490 490
491 void Assembler::ldrsh(Register rd, Address ad, Condition cond) { 491 void Assembler::ldrsh(Register rd, Address ad, Condition cond) {
492 EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad); 492 EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad);
493 } 493 }
494 494
495 495
496 void Assembler::ldrd(Register rd, Register rn, int32_t offset, Condition cond) { 496 void Assembler::ldrd(Register rd, Register rd2, Register rn, int32_t offset,
497 Condition cond) {
497 ASSERT((rd % 2) == 0); 498 ASSERT((rd % 2) == 0);
499 ASSERT(rd2 == rd + 1);
498 if (TargetCPUFeatures::arm_version() == ARMv5TE) { 500 if (TargetCPUFeatures::arm_version() == ARMv5TE) {
499 const Register rd2 = static_cast<Register>(static_cast<int32_t>(rd) + 1);
500 ldr(rd, Address(rn, offset), cond); 501 ldr(rd, Address(rn, offset), cond);
501 ldr(rd2, Address(rn, offset + kWordSize), cond); 502 ldr(rd2, Address(rn, offset + kWordSize), cond);
502 } else { 503 } else {
503 EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, Address(rn, offset)); 504 EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, Address(rn, offset));
504 } 505 }
505 } 506 }
506 507
507 508
508 void Assembler::strd(Register rd, Register rn, int32_t offset, Condition cond) { 509 void Assembler::strd(Register rd, Register rd2, Register rn, int32_t offset,
510 Condition cond) {
509 ASSERT((rd % 2) == 0); 511 ASSERT((rd % 2) == 0);
512 ASSERT(rd2 == rd + 1);
510 if (TargetCPUFeatures::arm_version() == ARMv5TE) { 513 if (TargetCPUFeatures::arm_version() == ARMv5TE) {
511 const Register rd2 = static_cast<Register>(static_cast<int32_t>(rd) + 1);
512 str(rd, Address(rn, offset), cond); 514 str(rd, Address(rn, offset), cond);
513 str(rd2, Address(rn, offset + kWordSize), cond); 515 str(rd2, Address(rn, offset + kWordSize), cond);
514 } else { 516 } else {
515 EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, Address(rn, offset)); 517 EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, Address(rn, offset));
516 } 518 }
517 } 519 }
518 520
519 521
520 void Assembler::ldm(BlockAddressMode am, Register base, RegList regs, 522 void Assembler::ldm(BlockAddressMode am, Register base, RegList regs,
521 Condition cond) { 523 Condition cond) {
(...skipping 1177 matching lines...) Expand 10 before | Expand all | Expand 10 after
1699 } 1701 }
1700 str(value, Address(base, offset), cond); 1702 str(value, Address(base, offset), cond);
1701 } 1703 }
1702 1704
1703 1705
1704 void Assembler::WriteShadowedFieldPair(Register base, 1706 void Assembler::WriteShadowedFieldPair(Register base,
1705 intptr_t offset, 1707 intptr_t offset,
1706 Register value_even, 1708 Register value_even,
1707 Register value_odd, 1709 Register value_odd,
1708 Condition cond) { 1710 Condition cond) {
1709 ASSERT(value_odd == value_even + 1); 1711 ASSERT(value_odd == value_even + 1);
zra 2015/10/23 03:48:44 assert value_even % 2 == 0.
rmacnak 2015/10/23 16:29:03 Done.
1710 if (VerifiedMemory::enabled()) { 1712 if (VerifiedMemory::enabled()) {
1711 ASSERT(base != value_even); 1713 ASSERT(base != value_even);
1712 ASSERT(base != value_odd); 1714 ASSERT(base != value_odd);
1713 Operand shadow(GetVerifiedMemoryShadow()); 1715 Operand shadow(GetVerifiedMemoryShadow());
1714 add(base, base, shadow, cond); 1716 add(base, base, shadow, cond);
1715 strd(value_even, base, offset, cond); 1717 strd(value_even, value_odd, base, offset, cond);
1716 sub(base, base, shadow, cond); 1718 sub(base, base, shadow, cond);
1717 } 1719 }
1718 strd(value_even, base, offset, cond); 1720 strd(value_even, value_odd, base, offset, cond);
1719 } 1721 }
1720 1722
1721 1723
1722 Register UseRegister(Register reg, RegList* used) { 1724 Register UseRegister(Register reg, RegList* used) {
1723 ASSERT(reg != SP); 1725 ASSERT(reg != SP);
1724 ASSERT(reg != PC); 1726 ASSERT(reg != PC);
1725 ASSERT((*used & (1 << reg)) == 0); 1727 ASSERT((*used & (1 << reg)) == 0);
1726 *used |= (1 << reg); 1728 *used |= (1 << reg);
1727 return reg; 1729 return reg;
1728 } 1730 }
(...skipping 1118 matching lines...) Expand 10 before | Expand all | Expand 10 after
2847 break; 2849 break;
2848 case kHalfword: 2850 case kHalfword:
2849 ldrsh(reg, Address(base, offset), cond); 2851 ldrsh(reg, Address(base, offset), cond);
2850 break; 2852 break;
2851 case kUnsignedHalfword: 2853 case kUnsignedHalfword:
2852 ldrh(reg, Address(base, offset), cond); 2854 ldrh(reg, Address(base, offset), cond);
2853 break; 2855 break;
2854 case kWord: 2856 case kWord:
2855 ldr(reg, Address(base, offset), cond); 2857 ldr(reg, Address(base, offset), cond);
2856 break; 2858 break;
2857 case kWordPair: 2859 case kWordPair: {
zra 2015/10/23 03:48:44 To retain the benefits of passing both registers t
rmacnak 2015/10/23 16:29:03 Deleted this case as it is unused.
2858 ldrd(reg, base, offset, cond); 2860 Register reg2 = static_cast<Register>(static_cast<int32_t>(reg) + 1);
2861 ldrd(reg, reg2, base, offset, cond);
2859 break; 2862 break;
2863 }
2860 default: 2864 default:
2861 UNREACHABLE(); 2865 UNREACHABLE();
2862 } 2866 }
2863 } 2867 }
2864 2868
2865 2869
2866 void Assembler::StoreToOffset(OperandSize size, 2870 void Assembler::StoreToOffset(OperandSize size,
2867 Register reg, 2871 Register reg,
2868 Register base, 2872 Register base,
2869 int32_t offset, 2873 int32_t offset,
2870 Condition cond) { 2874 Condition cond) {
2871 int32_t offset_mask = 0; 2875 int32_t offset_mask = 0;
2872 if (!Address::CanHoldStoreOffset(size, offset, &offset_mask)) { 2876 if (!Address::CanHoldStoreOffset(size, offset, &offset_mask)) {
2873 ASSERT(reg != IP); 2877 ASSERT(reg != IP);
2874 ASSERT(base != IP); 2878 ASSERT(base != IP);
2875 AddImmediate(IP, base, offset & ~offset_mask, cond); 2879 AddImmediate(IP, base, offset & ~offset_mask, cond);
2876 base = IP; 2880 base = IP;
2877 offset = offset & offset_mask; 2881 offset = offset & offset_mask;
2878 } 2882 }
2879 switch (size) { 2883 switch (size) {
2880 case kByte: 2884 case kByte:
2881 strb(reg, Address(base, offset), cond); 2885 strb(reg, Address(base, offset), cond);
2882 break; 2886 break;
2883 case kHalfword: 2887 case kHalfword:
2884 strh(reg, Address(base, offset), cond); 2888 strh(reg, Address(base, offset), cond);
2885 break; 2889 break;
2886 case kWord: 2890 case kWord:
2887 str(reg, Address(base, offset), cond); 2891 str(reg, Address(base, offset), cond);
2888 break; 2892 break;
2889 case kWordPair: 2893 case kWordPair: {
zra 2015/10/23 03:48:44 ditto
rmacnak 2015/10/23 16:29:03 Deleted
2890 strd(reg, base, offset, cond); 2894 Register reg2 = static_cast<Register>(static_cast<int32_t>(reg) + 1);
2895 strd(reg, reg2, base, offset, cond);
2891 break; 2896 break;
2897 }
2892 default: 2898 default:
2893 UNREACHABLE(); 2899 UNREACHABLE();
2894 } 2900 }
2895 } 2901 }
2896 2902
2897 2903
2898 void Assembler::LoadSFromOffset(SRegister reg, 2904 void Assembler::LoadSFromOffset(SRegister reg,
2899 Register base, 2905 Register base,
2900 int32_t offset, 2906 int32_t offset,
2901 Condition cond) { 2907 Condition cond) {
(...skipping 738 matching lines...) Expand 10 before | Expand all | Expand 10 after
3640 3646
3641 3647
3642 const char* Assembler::FpuRegisterName(FpuRegister reg) { 3648 const char* Assembler::FpuRegisterName(FpuRegister reg) {
3643 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); 3649 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
3644 return fpu_reg_names[reg]; 3650 return fpu_reg_names[reg];
3645 } 3651 }
3646 3652
3647 } // namespace dart 3653 } // namespace dart
3648 3654
3649 #endif // defined TARGET_ARCH_ARM 3655 #endif // defined TARGET_ARCH_ARM
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