Generate block labels in the ARM hybrid assembler.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 06ba9c466e55a85a98b74024c3b66229b3117ce8..7f9e50946063bb651cdcfdc54e44a22c5d55aa2b 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -21,6 +21,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "IceAssemblerARM32.h"
+#include "IceCfgNode.h"
 #include "IceUtils.h"
 
 namespace {
@@ -204,6 +205,17 @@ DecodedResult decodeAddress(const Operand *Opnd, uint32_t &Value) {
 
 namespace Ice {
 
+void ARM32::AssemblerARM32::bindCfgNodeLabel(const CfgNode *Node) {
+  if (BuildDefs::dump() && !Ctx->getFlags().getDisableHybridAssembly()) {
+    // Generate label name so that branches can find it.
+    emitTextInst(Node->getAsmName() + ":", 0);

[Jim Stichnoth, 2015/10/23 13:54:52]

Can you use "constexpr SizeT InstSize = 0;" for the "0" arg?

[Karl, 2015/10/23 16:20:07]

Done.

+  }
+  SizeT NodeNumber = Node->getIndex();
+  assert(!getPreliminary());
+  Label *L = getOrCreateCfgNodeLabel(NodeNumber);
+  this->bind(L);
+}
+
 Label *ARM32::AssemblerARM32::getOrCreateLabel(SizeT Number,
                                                LabelVector &Labels) {
   Label *L = nullptr;
@@ -236,12 +248,13 @@ void ARM32::AssemblerARM32::bind(Label *label) {
   label->bindTo(bound);
 }
 
-void ARM32::AssemblerARM32::emitTextInst(const std::string &Text) {
-  static constexpr uint32_t Placeholder = 0;
+void ARM32::AssemblerARM32::emitTextInst(const std::string &Text,
+                                         SizeT InstSize) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
-  AssemblerFixup *F = createTextFixup(Text, sizeof(Placeholder));
+  AssemblerFixup *F = createTextFixup(Text, InstSize);
   emitFixup(F);
-  emitInst(Placeholder);
+  for (SizeT I = 0; I < InstSize; ++I)
+    Buffer.emit<char>(0);
 }
 
 void ARM32::AssemblerARM32::emitType01(CondARM32::Cond Cond, uint32_t Type,