Subzero: Fix MINIMAL build issues.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 110 matching lines @@
 DecodedResult decodeOperand(const Operand *Opnd, uint32_t &Value) {
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     if (Var->hasReg()) {
       Value = Var->getRegNum();
       return DecodedAsRegister;
     }
   } else if (const auto *FlexImm = llvm::dyn_cast<OperandARM32FlexImm>(Opnd)) {
     const uint32_t Immed8 = FlexImm->getImm();
     const uint32_t Rotate = FlexImm->getRotateAmt();
     assert((Rotate < (1 << kRotateBits)) && (Immed8 < (1 << kImmed8Bits)));
+    // TODO(kschimpf): Remove void casts when MINIMAL build allows.
+    (void) kRotateBits;
+    (void) kImmed8Bits;
     Value = (Rotate << kRotateShift) | (Immed8 << kImmed8Shift);
     return DecodedAsRotatedImm8;
   }
   return CantDecode;
 }
 
 uint32_t decodeImmRegOffset(RegARM32::GPRRegister Reg, int32_t Offset,
                             OperandARM32Mem::AddrMode Mode) {
   uint32_t Value = Mode | (encodeGPRRegister(Reg) << kRnShift);
   if (Offset < 0) {
@@ skipping 54 matching lines @@
     label->setPosition(next);
   }
   // TODO(kschimpf) Decide if we have near jumps.
   label->bindTo(bound);
 }
 
 void ARM32::AssemblerARM32::emitType01(CondARM32::Cond Cond, uint32_t Type,
                                        uint32_t Opcode, bool SetCc, uint32_t Rn,
                                        uint32_t Rd, uint32_t Imm12) {
   assert(isGPRRegisterDefined(Rd));
+  // TODO(kschimpf): Remove void cast when MINIMAL build allows.
+  (void) isGPRRegisterDefined(Rd);
   assert(Cond != CondARM32::kNone);
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const uint32_t Encoding = (encodeCondition(Cond) << kConditionShift) |
                             (Type << kTypeShift) | (Opcode << kOpcodeShift) |
                             (encodeBool(SetCc) << kSShift) | (Rn << kRnShift) |
                             (Rd << kRdShift) | Imm12;
   emitInst(Encoding);
 }
 
 void ARM32::AssemblerARM32::emitMemOp(CondARM32::Cond Cond, uint32_t InstType,
@@ skipping 42 matching lines @@
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const uint32_t Encoding = (CondARM32::AL << kConditionShift) | B24 | B21 |
                             ((imm16 >> 4) << 8) | B6 | B5 | B4 | (imm16 & 0xf);
   emitInst(Encoding);
 }
 
 void ARM32::AssemblerARM32::bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond) {
   // cccc000100101111111111110001mmmm where mmmm=rm and cccc=Cond.
   // (ARM section A8.8.27, encoding A1).
   assert(isGPRRegisterDefined(Rm));
+  // TODO(kschimpf): Remove void cast when MINIMAL build allows.
+  (void) isGPRRegisterDefined(Rm);
   assert(isConditionDefined(Cond));
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const uint32_t Encoding = (encodeCondition(Cond) << kConditionShift) | B24 |
                             B21 | (0xfff << 8) | B4 |
                             (encodeGPRRegister(Rm) << kRmShift);
   emitInst(Encoding);
 }
 
 void ARM32::AssemblerARM32::ldr(const Operand *OpRt, const Operand *OpAddress,
                                 CondARM32::Cond Cond) {
@@ skipping 109 matching lines @@
       constexpr uint32_t Add = B1; // 0010
       constexpr uint32_t InstType = 1;
       emitType01(Cond, InstType, Add, SetFlags, Rn, Rd, Src1Value);
       return;
     }
   } while (0);
   UnimplementedError(Ctx->getFlags());
 }
 
 } // end of namespace Ice