Subzero. Misc ARM32 bugfixes.

src/IceTargetLoweringARM32.cpp

Index: src/IceTargetLoweringARM32.cpp
diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index 2615b36c6c4236daaee55fa4250ef90b1080bc30..0aa8d7e81c9a4f7f9759a8ca5fe83b7c47a1893a 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -742,7 +742,9 @@ void TargetARM32::addProlog(CfgNode *Node) {
       // TODO(jvoung): do separate vpush for each floating point register
       // segment and += 4, or 8 depending on type.
       ++NumCallee;
-      PreservedRegsSizeBytes += 4;
+      Variable *PhysicalRegister = getPhysicalRegister(i);
+      PreservedRegsSizeBytes +=
+          typeWidthInBytesOnStack(PhysicalRegister->getType());
       GPRsToPreserve.push_back(getPhysicalRegister(i));
     }
   }
@@ -1628,15 +1630,15 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
   default:
     break;
   case InstArithmetic::Udiv: {
-    constexpr bool IsRemainder = false;
+    constexpr bool NotRemainder = false;
     lowerIDivRem(Dest, T, Src0R, Src1, &TargetARM32::_uxt, &TargetARM32::_udiv,
-                 H_udiv_i32, IsRemainder);
+                 H_udiv_i32, NotRemainder);
     return;
   }
   case InstArithmetic::Sdiv: {
-    constexpr bool IsRemainder = false;
+    constexpr bool NotRemainder = false;
     lowerIDivRem(Dest, T, Src0R, Src1, &TargetARM32::_sxt, &TargetARM32::_sdiv,
-                 H_sdiv_i32, IsRemainder);
+                 H_sdiv_i32, NotRemainder);
     return;
   }
   case InstArithmetic::Urem: {
@@ -1730,10 +1732,16 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
     _mov(Dest, T);
     return;
   case InstArithmetic::Lshr:
+    if (Dest->getType() != IceType_i32) {
+      _uxt(Src0R, Src0R);
+    }
     _lsr(T, Src0R, Src1RF);
     _mov(Dest, T);
     return;
   case InstArithmetic::Ashr:
+    if (Dest->getType() != IceType_i32) {
+      _sxt(Src0R, Src0R);
+    }
     _asr(T, Src0R, Src1RF);
     _mov(Dest, T);
     return;
@@ -1804,6 +1812,9 @@ void TargetARM32::lowerBr(const InstBr *Inst) {
   // TODO(jvoung): Handle folding opportunities.
 
   Variable *Src0R = legalizeToReg(Cond);
+  assert(Src0R->mustHaveReg());
+  if (Src0R->getType() != IceType_i32)

[Jim Stichnoth, 2015/10/15 23:34:21]

Won't it always be the case that Src0R->getType() == IceType_i1 ?

[John, 2015/11/05 20:25:13]

maybe, but better safe than sorry. I left an assert for quick test failure, but
I left the if here.

+    _uxt(Src0R, Src0R);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   _cmp(Src0R, Zero);
   _br(Inst->getTargetTrue(), Inst->getTargetFalse(), CondARM32::NE);
@@ -2298,6 +2309,8 @@ void TargetARM32::lowerCast(const InstCast *Inst) {
       configureBitcastTemporary(T);
       Variable *Src0R = legalizeToReg(Src0);
       _mov(T, Src0R);
+      Context.insert(InstFakeUse::create(Func, T->getHi()));
+      Context.insert(InstFakeUse::create(Func, T->getLo()));
       lowerAssign(InstAssign::create(Func, Dest, T));
       break;
     }
@@ -3248,9 +3261,7 @@ void TargetARM32::lowerLoad(const InstLoad *Load) {
   lowerAssign(Assign);
 }
 
-void TargetARM32::doAddressOptLoad() {
-  UnimplementedError(Func->getContext()->getFlags());
-}
+void TargetARM32::doAddressOptLoad() {}
 
 void TargetARM32::randomlyInsertNop(float Probability,
                                     RandomNumberGenerator &RNG) {
@@ -3321,6 +3332,8 @@ void TargetARM32::lowerSelect(const InstSelect *Inst) {
   // cmp cond, #0; mov t, SrcF; mov_cond t, SrcT; mov dest, t
   Variable *CmpOpnd0 = legalizeToReg(Condition);
   Operand *CmpOpnd1 = Ctx->getConstantZero(IceType_i32);
+  if (CmpOpnd0->getType() != IceType_i32)

[Jim Stichnoth, 2015/10/15 23:34:21]

Same comment as above -- isn't the type always IceType_i1?

[John, 2015/11/05 20:25:13]

Done.

+    _uxt(CmpOpnd0, CmpOpnd0);
   _cmp(CmpOpnd0, CmpOpnd1);
   static constexpr CondARM32::Cond Cond = CondARM32::NE;
   if (DestTy == IceType_i64) {
@@ -3384,9 +3397,7 @@ void TargetARM32::lowerStore(const InstStore *Inst) {
   }
 }
 
-void TargetARM32::doAddressOptStore() {
-  UnimplementedError(Func->getContext()->getFlags());
-}
+void TargetARM32::doAddressOptStore() {}
 
 void TargetARM32::lowerSwitch(const InstSwitch *Inst) {
   // This implements the most naive possible lowering.
@@ -3410,10 +3421,21 @@ void TargetARM32::lowerSwitch(const InstSwitch *Inst) {
     return;
   }
 
-  // 32 bit integer
   Variable *Src0Var = legalizeToReg(Src0);
+  // If Src0 is not an i32, we left shift it -- see the icmp lowering for the
+  // reason.
+  assert(Src0Var->mustHaveReg());
+  const size_t ShiftAmt = 32 - getScalarIntBitWidth(Src0->getType());
+  assert(ShiftAmt < 32);
+  if (ShiftAmt > 0) {
+    Operand *ShiftConst = Ctx->getConstantInt32(ShiftAmt);
+    Variable *T = makeReg(IceType_i32);
+    _lsl(T, Src0Var, ShiftConst);
+    Src0Var = T;
+  }
+
   for (SizeT I = 0; I < NumCases; ++I) {
-    Operand *Value = Ctx->getConstantInt32(Inst->getValue(I));
+    Operand *Value = Ctx->getConstantInt32(Inst->getValue(I) << ShiftAmt);
     Value = legalize(Value, Legal_Reg | Legal_Flex);
     _cmp(Src0Var, Value);
     _br(Inst->getLabel(I), CondARM32::EQ);